Backside Feedthrough Wiring for Low-Resistance Semiconductor Routing
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Solution Overview
Problem
As semiconductor devices shrink in size, the backside conductive patterns used for connecting frontside patterns via through-silicon-via (TSV) or other means face challenges in achieving low electrical resistance due to their larger width and thickness compared to frontside patterns, which complicates efficient signal routing and increases resistance and capacitance in the circuit layout.
Innovation Solution
The implementation of a semiconductor device manufacturing process that includes a backside wiring structure with feedthrough vias and frontside wiring layers, allowing signals to be routed efficiently between FETs, reducing resistance and capacitance, and enhancing circuit layout flexibility by forming backside and frontside contacts and wiring patterns that connect the source/drain regions of FETs across the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside conductive patterns are made wider and thicker to reduce electrical resistance, then electrical resistance decreases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent utilizes the backside of the semiconductor substrate as a new dimension for wiring routing. By forming backside conductive patterns on the rear surface of the substrate and connecting them to frontside patterns through through-substrate vias, the invention creates a three-dimensional wiring architecture that reduces resistance without increasing planar complexity on the frontside.
Solution Approach 2:
The wiring structure is segmented into frontside conductive patterns, backside conductive patterns, and connecting via structures. This segmentation allows independent optimization of each component: frontside patterns maintain standard dimensions, backside patterns provide low-resistance paths with greater width and thickness, and vias provide vertical interconnection, thereby resolving the contradiction between resistance reduction and complexity management.
2Reliability
If backside conductive patterns are used for signal routing, then electrical connectivity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the backside conductive patterns and via structures before finalizing the frontside wiring. The backside patterns are deposited and patterned first, establishing a stable foundation that guides subsequent via formation and frontside pattern integration. This preliminary action reduces the precision burden on later manufacturing steps.
Solution Approach 2:
The via structures serve as intermediaries that connect the frontside and backside conductive patterns. These vias are designed with sufficient diameter and optimized positioning to tolerate normal manufacturing variations, acting as robust mediators that ensure reliable electrical connectivity without requiring extreme alignment precision.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.