Self-Powered Cascode Switching Module for GaN Reliability

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Solution Overview

Problem

State-of-the-art cascode switching modules using GaN devices face issues with reliability degradation due to parasitic inductances and capacitance mismatch, leading to oscillations and increased power losses, and require external gate drivers and bleeder resistors, which complicate hardware implementation and reduce efficiency.

Innovation Solution

A cascode switching module with a normally-on GaN device and a normally-off MOSFET, integrated with a self-powered gate driver that minimizes parasitic inductances and noise, utilizing energy harvesting and internal power generation to control midpoint voltage and reduce power losses, eliminating the need for external gate driver power supplies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large capacitor CX is integrated into the MOSFET die to mitigate middle point voltage overshoot, then reliability is improved, but power loss increases and chip size increases

Engineering Contradiction:
ImproveGaN gate reliabilityVSAvoidpower loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The gate driver circuit is designed to self-power from the GaN device drain-source voltage during operation, eliminating the need for external power supply and associated capacitors. The circuit harvests energy from the switching operations themselves to drive the gate, making the system self-sufficient and removing the source of power loss.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent extracts and removes the large capacitor CX from the MOSFET die integration, eliminating the component that causes both reliability improvement and power loss. Instead, a minimal capacitor is used in the self-powered gate driver circuit, removing the trade-off entirely.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If a bleeder resistor RX is integrated into the MOSFET die to sink GaN leakage current, then reliability is improved, but efficiency deteriorates

Engineering Contradiction:
Improvecascode device stabilityVSAvoidefficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The gate driver circuit uses the GaN device's own drain-source voltage to power itself, eliminating the need for external power supply components including bleeder resistors. The circuit naturally manages the GaN leakage current through its self-powered operation without requiring additional current-sinking components.

Inventive Principle:
Principle #25Self-service

3Ease of operation

If external gate drivers and bleeder resistors are used, then device functionality is achieved, but device complexity increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidhardware complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges the gate driver circuit, power management, and protection functions into a single integrated self-powered circuit block that works directly with the cascode device. This consolidation eliminates external gate drivers and bleeder resistors, reducing hardware complexity while maintaining full device functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The self-powered gate driver circuit performs multiple functions simultaneously: driving the gate, managing power, protecting against voltage overshoot, and handling leakage current. This multi-functional integration replaces multiple separate components, simplifying the overall system.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240178831A1Cascode Switching Module
Publication Date: 2024.05.30 NEXPERIA BV
  • US20240178831A1 patent drawing
  • US20240178831A1 patent drawing
  • US20240178831A1 patent drawing

AI summary

A cascode transistor circuit including a depletion mode semiconductor device, an enhancement mode transistor having a drain terminal connected to a source terminal of the depletion mode semiconductor device, and a gate driver coupled to a first node between the source of the depletion mode semiconductor device and the drain of the enhancement mode transistor. The gate driver is powered by the depletion mode semiconductor device.