Nonvolatile Memory Device With Non-Uniform Dielectric Thickness

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Solution Overview

Problem

In three-dimensional semiconductor memory devices, the high integration of memory cells leads to a large aspect ratio of memory holes, resulting in tapered side surfaces and varying diameters, which affects the electric field intensity and memory cell characteristics, making it challenging to maintain uniformity and reliability.

Innovation Solution

A nonvolatile semiconductor memory device with a stacked body of alternately arranged dielectric and electrode films, featuring a thicker dielectric film in the center portion and a thicker electrode film in the end portion, along with semiconductor pillars and a charge storage layer, and plugs connected to the electrode films, to ensure uniform memory cell formation and reduced interconnect resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of stacked electrode films is increased to achieve high integration density, then the integration density is improved, but the aspect ratio of memory holes becomes large and manufacturing complexity increases

Engineering Contradiction:
Improveintegration densityVSAvoidaspect ratio of memory hole
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies local quality by making the dielectric film thickness non-uniform: the center portion has a larger thickness than the end portion. This local variation in dielectric film thickness compensates for the tapered shape of memory holes, maintaining uniform electric field distribution across different regions of the stacked body, thereby enabling high integration density while managing the large aspect ratio of memory holes.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the physical parameter of dielectric film thickness from uniform to non-uniform distribution. Specifically, the center portion thickness is increased relative to the end portion thickness. This parameter change addresses the electric field non-uniformity caused by the large aspect ratio of memory holes, allowing for higher integration density without compromising device performance.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If the number of stacked electrode films is increased to achieve high integration density, then the integration density is improved, but manufacturing cost increases

Engineering Contradiction:
Improveintegration densityVSAvoidmanufacturing cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent implements local quality through selective thickness variation of the dielectric film, where the center portion is thicker than the end portion. This approach maintains uniform electric field characteristics across the stacked body, enabling reliable operation at high integration densities without requiring additional complex manufacturing steps, thus controlling manufacturing cost.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent modifies the dielectric film thickness parameter from a constant value to a spatially varying value (thicker at center, thinner at ends). This parameter change optimizes the electric field distribution to accommodate high integration density requirements while using standard manufacturing processes, avoiding increased manufacturing cost.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If memory holes are formed in a thick stacked body with large aspect ratio, then high integration density is achieved, but the diameter of memory hole varies and electric field uniformity deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoiduniformity of memory hole diameter
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating a non-uniform dielectric film thickness profile: the center portion has larger thickness than the end portion. This local variation compensates for the tapered geometry of memory holes formed in the thick stacked body, ensuring that the electric field intensity remains uniform across different regions, thereby maintaining manufacturing precision despite the large aspect ratio.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the dielectric film thickness parameter from uniform to non-uniform distribution, with the center portion being thicker. This parameter modification compensates for the geometric tapering of memory holes, maintaining consistent electric field characteristics and uniform memory cell performance throughout the stacked body, even when memory holes have large aspect ratios.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for uniform memory cell characteristics, reduced interconnect resistance, and improved data retention by maintaining a consistent electric field across memory cells, enhancing the integration density and manufacturing efficiency.

Implementation Method 1

a portion of each of the dielectric films in the center portion having a larger thickness than a portion of each of the dielectric films in the end portion

Methodology Applied
Scientific EffectDielectric: Dielectric

Data Source

PatentUS8247860B2Nonvolatile semiconductor memory device and method for manufacturing same
Publication Date: 2012.08.21 KIOXIA CORP
  • US8247860B2 patent drawing
  • US8247860B2 patent drawing
  • US8247860B2 patent drawing

AI summary

A nonvolatile semiconductor memory device includes: a substrate; a stacked body with a plurality of dielectric films and electrode films alternately stacked therein, the stacked body being provided on the substrate and having a step in its end portion for each of the electrode films; an interlayer dielectric film burying the end portion of the stacked body; a plurality of semiconductor pillars extending in the stacking direction of the stacked body and penetrating through a center portion of the stacked body; a charge storage layer provided between one of the electrode films and one of the semiconductor pillars; and a plug buried in the interlayer dielectric film and connected to a portion of each of the electrode films constituting the step, a portion of each of the dielectric films in the center portion having a larger thickness than a portion of each of the dielectric films in the end portion.