Monocrystalline Bottom-Gate 3DIC Transistors for Low-Temperature Integration
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Solution Overview
Problem
The challenge in monolithic 3D integrated circuit (3DIC) fabrication is the need for low-temperature processing to prevent degradation of previously fabricated device levels, which limits the use of high-k gate dielectric materials and results in lower carrier mobility and higher variability due to the use of amorphous or polycrystalline semiconductor materials.
Innovation Solution
The integration of a monocrystalline channel material over a bottom gate stack with a high-k gate dielectric, achieved through low-temperature epitaxial growth of source and drain material and layer transfer techniques, allowing for precise patterning and alignment with lower-level circuitry, enabling higher channel mobility and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-temperature processing is used to prevent degradation of previously fabricated device levels, then monolithic 3DIC fabrication is enabled, but carrier mobility decreases and variability increases due to use of amorphous or polycrystalline semiconductor materials
Solution Approach 1:
The patent changes the crystalline state parameter of the semiconductor channel material from amorphous/polycrystalline to monocrystalline, enabling high carrier mobility to be achieved at low processing temperatures. This is accomplished through selective epitaxial growth that forms monocrystalline semiconductor regions over the gate electrode, allowing the channel material to maintain high mobility without requiring high-temperature processing.
2Object-generated harmful factors
If high-k gate dielectric materials are used to reduce device leakage, then off-state leakage decreases, but thermal annealing is required which exceeds the low-temperature threshold and degrades previously fabricated device levels
Solution Approach 1:
The patent performs preliminary formation of the gate dielectric layer and gate electrode structure before forming the monocrystalline semiconductor channel material. This allows the gate stack to be prepared in advance, and the subsequent low-temperature epitaxial growth to complete the transistor structure without requiring high-temperature annealing that would degrade previously fabricated levels.
Solution Approach 2:
The patent introduces a gate electrode as an intermediary element between the gate dielectric and the semiconductor channel. This gate electrode structure enables the use of high-k gate dielectric materials while avoiding the need for high-temperature thermal annealing, as the epitaxial growth process can form the monocrystalline channel at low temperatures without requiring subsequent high-temperature processing steps.
3Temperature
If amorphous or polycrystalline semiconductor materials are used for low-temperature fabrication, then processing temperature remains below 450°C, but manufacturing precision decreases due to higher variability in device characteristics
Solution Approach 1:
The patent changes the crystalline structure parameter of the semiconductor channel material from amorphous or polycrystalline to monocrystalline through selective epitaxial growth. This structural transformation maintains compatibility with low-temperature processing (below 450°C) while dramatically improving manufacturing precision by reducing device variability, as monocrystalline materials provide more uniform and predictable electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and reliability of upper-level transistors by maintaining high channel mobility and reducing device leakage, while allowing for finer alignment and higher IC density in monolithic 3DICs.
Implementation Method 1
low-temperature epitaxial growth of source and drain material
Data Source
AI summary
A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.