Stacked Nanosheet FETs with Horizontal Spacing Constraints
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Solution Overview
Problem
Conventional vertical finFET devices face challenges in scaling to smaller dimensions due to difficulties in forming metal thicknesses between adjacent fins, leading to issues with gate resistance and operational performance, particularly in achieving proper gate control and threshold voltage.
Innovation Solution
The development of field-effect transistors with stacked nanosheets, where horizontal spacing between nanosheets is minimized to enable a larger effective conduction width, using a gate stack that includes a low resistance gate metal layer and work function tuning metal, with a gate dielectric material extending continuously between nanosheets, allowing for improved channel conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If vertical fins are placed closer together to increase effective conduction width in a small layout area, then the effective channel conduction width is improved, but the gate resistance increases and operational performance deteriorates due to insufficient metal thickness between adjacent fins
Solution Approach 1:
The patent transitions from a planar 2D fin structure to a 3D stacked nanosheet structure. Multiple nanosheets are stacked vertically to form channel patterns, enabling the gate to control multiple channel layers simultaneously. This vertical stacking allows achieving larger effective conduction width without proportionally reducing lateral spacing, as the gate structure extends vertically to encompass multiple nanosheet layers.
Solution Approach 2:
The gate structure is designed to surround and encompass multiple nanosheet channels in a nested configuration. The gate dielectric and metal layers wrap around each nanosheet stack, creating a nested arrangement where the gate contains multiple channel layers within its structure. This allows efficient use of vertical space and maintains proper gate control over multiple channels.
2Area of stationary object
If the horizontal spacing between adjacent vertical fins is reduced to minimize layout area, then the area efficiency is improved, but it becomes difficult to form proper metal thicknesses for work-function tuning and low-resistance capping
Solution Approach 1:
The invention moves from lateral (horizontal) arrangement of channels to vertical stacking of nanosheets. This dimensional change allows the metal layers to be formed with adequate thickness in the vertical dimension while maintaining small lateral footprint. The gate metal layers can properly form around the vertically stacked nanosheets without the severe spacing constraints that would exist in a purely lateral arrangement.
Solution Approach 2:
The gate structure employs composite material layers including gate dielectric, work-function tuning metal, and low-resistance capping metal, each with optimized thickness in the vertical stacking direction. This composite structure allows each material layer to be properly formed with appropriate thickness, even when horizontal spacing is minimized, because the formation process occurs in the vertical dimension where more space is available.
3Reliability
If vertical fin height is increased to about 35-50 nm to achieve proper gate control, then the gate control of channel potential is improved, but the manufacturing complexity increases due to difficulty in forming metal layers along the full height
Solution Approach 1:
The channel is segmented into multiple discrete nanosheets stacked vertically, each surrounded by its own gate structure. This segmentation allows the gate metal layers to be formed in manageable sections around each nanosheet or nanosheet stack, rather than requiring continuous metal formation along a single tall fin structure. The segmentation reduces the effective height that metal layers must span continuously.
Solution Approach 2:
The gate structure is nested around each nanosheet stack, with the gate dielectric and metal layers forming concentric layers around the channel. This nested configuration allows metal layers to be deposited and formed in a controlled manner around the vertical stack, with each metal layer properly conforming to the underlying structure without requiring excessive vertical continuity that would increase manufacturing complexity.
Data Source
AI summary
A device including a stacked nanosheet field effect transistor (FET) may include a substrate, a first channel pattern on the substrate, a second channel pattern on the first channel pattern, a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and source/drain regions on opposing ends of the first channel pattern and second channel pattern. The first and second channel patterns may each include a respective plurality of nanosheets arranged in a respective horizontal plane that is parallel to a surface of the substrate. The nanosheets may be spaced apart from each other at a horizontal spacing distance between adjacent ones of the nanosheets. The second channel pattern may be spaced apart from the first channel pattern at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance.