Pillar-Shaped Semiconductor Layers Vertical Stacking
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Solution Overview
Problem
The miniaturization of MOS transistors in semiconductor integrated circuits leads to increased leak current and difficulty in reducing the occupied area, as existing surround gate transistors require significant space due to the need for multiple silicon pillars and complex gate structures.
Innovation Solution
A semiconductor device is designed with vertically stacked transistors, where multiple conductivity-type semiconductor layers and gate structures are formed on a substrate, allowing for the connection of gates and output terminals in a way that reduces the overall area by enabling vertical stacking and shared lithography steps for doping, particularly utilizing nMOS and pMOS layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If MOS transistors are miniaturized to increase integration degree, then the occupied area is reduced, but leak current increases and current requirement becomes harder to satisfy
Solution Approach 1:
The patent transitions from planar transistor arrangement to vertical stacking configuration. Multiple transistors are stacked in the vertical direction above the substrate, changing the spatial dimension from 2D to 3D. This allows higher integration density while maintaining adequate current characteristics, as each transistor retains its functional integrity in the vertical stack.
Solution Approach 2:
The patent implements nested structure where gate electrodes surround pillar-shaped semiconductor layers in a concentric arrangement. The gate electrode is positioned around the semiconductor pillar, creating a surrounding gate configuration that effectively controls the channel while maintaining compact footprint. Multiple such nested structures are then stacked vertically.
2Reliability
If surround gate transistors are used to control leak current, then current control is improved, but the area occupied increases due to multiple silicon pillars and complex gate structures
Solution Approach 1:
The patent resolves the area conflict by stacking multiple surround gate transistors vertically in the third dimension. Instead of arranging transistors side-by-side in the planar direction, they are positioned at different heights above the substrate, connected via vertical conductors. This vertical stacking maintains the leak current control benefits of surround gate structures while dramatically reducing the planar footprint.
Solution Approach 2:
The patent makes the vertical stack structure serve multiple functions: it provides electrical connection between stacked transistors, enables shared gate control, and reduces overall device area. The same vertical stacking approach is used for both nMOS and pMOS transistors, creating a universal integration scheme that handles both transistor types efficiently within the same three-dimensional framework.
3Productivity
If multiple transistors are formed on a plane to achieve integration, then integration is achieved, but the area required increases and vertical stacking becomes necessary for further integration
Solution Approach 1:
The patent achieves high integration by moving from planar to vertical arrangement. Transistors are stacked in multiple layers above the substrate, with conductors extending vertically to interconnect them. This three-dimensional integration allows many more transistors to be packed into a small planar area, dramatically increasing integration density without proportionally increasing the chip footprint.
Data Source
AI summary
A semiconductor device includes a first pillar-shaped semiconductor layer in which a second first-conductivity-type semiconductor layer, a first body region, a third first-conductivity-type semiconductor layer, a fourth first-conductivity-type semiconductor layer, a second body region, a fifth first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a third body region, and a second second-conductivity-type semiconductor layer are formed from a substrate side in this order; first, second, and third gates formed around first, second, third gate insulating films formed around the first, second, and third body regions, respectively; a first output terminal connecting the fifth first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer; a second pillar-shaped semiconductor layer, on the first output terminal, in which a third second-conductivity-type semiconductor layer, a fourth body region, and a fourth second-conductivity-type semiconductor layer are formed from the substrate side in this order; and a fourth gate insulating film formed around the fourth body region.