Gate Cut and Fin Trim Isolation for Sub-10nm Fin Scaling
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Solution Overview
Problem
The scaling of integrated circuits to the 10 nanometer node and beyond is hindered by variability in conventional fabrication processes, limiting the ability to further miniaturize semiconductor features and optimize device performance.
Innovation Solution
The implementation of pitch quartering and merged fin pitch quartering approaches in semiconductor fabrication, combined with advanced trench isolation and fin trim processes, to create more densely packed and stress-induced semiconductor fins, enabling improved transistor density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but feature size scaling to 10nm and below is limited due to process variability
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including pitch doubling, pitch quartering, and merged fin pitch quartering. Each stage breaks down the complex task of creating sub-10nm features into manageable steps with intermediate patterning and etching operations, allowing precise control at each phase rather than attempting single-step patterning
Solution Approach 2:
Mandrel structures are formed in advance before the final fin structures are created. These preliminary mandrels serve as templates for subsequent spacer formation and pattern transfer, enabling precise feature definition through preparatory patterning steps that establish the geometric framework for final device structures
2Productivity
If pitch quartering and merged fin pitch quartering are implemented, then transistor density is increased, but device complexity increases
Solution Approach 1:
Multiple patterning cycles are nested within each other, where spacers are formed around mandrels, then mandrels are removed and new spacers are formed around the first spacers. This nested approach allows fourfold pitch multiplication through sequential spacer formation, enabling high transistor density while organizing the complex process into repeatable modular units
Solution Approach 2:
The fabrication process transitions from two-dimensional planar patterning to three-dimensional fin structures through vertical etching. Merged fin pitch quartering creates fins with controlled heights and widths by combining horizontal spacer patterning with vertical anisotropic etching, adding the height dimension to the density equation
3Stress or pressure
If advanced trench isolation and fin trim processes are used, then fin stress control is improved, but manufacturing complexity increases
Solution Approach 1:
Trench isolation structures are formed with different depths and fill materials in different device regions. Shallow trenches with silicon nitride fill are used in some areas while deeper trenches with oxide fill are used in others, allowing localized stress optimization for specific transistor types or circuit functions without affecting the entire wafer uniformly
Solution Approach 2:
The fin trim process dynamically adjusts fin dimensions by controlling etch depth and duration based on desired stress characteristics. By varying etch parameters and isolation trench depths, the process optimizes fin stress states to enhance carrier mobility and device performance for different circuit requirements
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.