FinFET Contact Trench Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling integrated circuit density and effectively suppressing short channel effects while maintaining current control, particularly in multi-gate transistors with fin-shaped or nanowire-shaped silicon bodies.
Innovation Solution
A semiconductor device design featuring fin-type patterns with intersecting gate electrodes, source/drain regions, and a separation structure with trenches, where the interlayer insulating layer covers the source/drain regions and the separation structure, allowing for precise contact formation that reduces parasitic capacitance and enhances performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors with fin-shaped or nanowire-shaped silicon bodies are used to increase integrated circuit density, then scaling is easily performed and current control capability is improved, but short channel effects may still affect the channel region potential due to drain voltage
Solution Approach 1:
The gate electrode is divided into multiple segments along the channel length, creating multiple gate regions that can independently control different portions of the channel. This segmentation allows for optimized electric field distribution that suppresses short channel effects while maintaining high density multi-gate transistor performance
Solution Approach 2:
Different regions of the gate electrode are configured with different characteristics (such as varying widths, materials, or doping levels) to provide localized control over the channel. This enables tailored electric field profiles that effectively suppress short channel effects in critical regions while maintaining overall high density
2Reliability
If the gate electrode is separated into multiple regions, then short channel effects are suppressed, but the device structure becomes more complex
Solution Approach 1:
The segmented gate electrode structure serves multiple functions simultaneously: it suppresses short channel effects through regional control, maintains manufacturing compatibility with existing processes, and enables optimized current control. This multi-functionality reduces the need for additional separate structures, thereby limiting complexity increase
3Reliability
If contact holes are formed to connect to source/drain regions, then electrical connection is established, but parasitic capacitance increases and performance is degraded
Solution Approach 1:
The contact structure is extracted or removed from directly overlying the source/drain regions. Instead, contacts are positioned in alternative locations that maintain electrical connection while eliminating the parasitic capacitance that would be introduced by contacts directly above the active source/drain regions
Data Source
AI summary
A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.