Multi-Level SONOS Memory Stack With Angled LDD for Analog Storage
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Solution Overview
Problem
Current non-volatile memory technologies, such as SONOS, primarily support binary data storage and lack the capability to efficiently store multiple analog values, which is essential for advanced applications like neuromorphic computing and edge inference computations that require precise multi-level threshold voltages and drain currents.
Innovation Solution
Integration of multi-level SONOS cell fabrication into the baseline CMOS process flow, utilizing angled lightly doped drain implants and optimized oxide-nitride-oxide layers to minimize gate-induced drain leakage and achieve precise control over threshold voltages and drain currents, enabling storage of multiple analog values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SONOS memory cells are used for binary data storage, then reliability is improved, but adaptability deteriorates due to inability to store multiple analog values
Solution Approach 1:
The patent applies parameter changes by modifying the threshold voltage (Vt) of SONOS memory cells through controlled charge trapping. By varying the amount of charge trapped in the oxide-nitride-oxide layer during fabrication and operation, the memory cells can achieve multiple distinct Vt levels (e.g., 4, 8, or 16 levels), enabling analog value storage while maintaining the reliability of SONOS technology. This is accomplished through precise control of tunneling currents and charge injection during programming operations.
2Ease of manufacture
If multi-level SONOS cell fabrication is integrated into baseline CMOS process flow, then ease of manufacture is improved, but manufacturing precision must be enhanced to achieve precise control over threshold voltages and drain currents
Solution Approach 1:
The patent employs parameter changes through precise control of fabrication parameters including oxide layer thicknesses, nitride layer composition, doping concentrations, and thermal processing conditions. These parameter adjustments enable precise control over the charge trapping characteristics and threshold voltage levels during CMOS-compatible fabrication, achieving the required manufacturing precision for multi-level analog storage.
Solution Approach 2:
The patent implements feedback mechanisms through iterative measurement and adjustment of threshold voltages and drain currents during the fabrication process. By monitoring these parameters and adjusting subsequent processing steps accordingly, the method achieves precise control over the final memory cell characteristics while maintaining compatibility with standard CMOS manufacturing workflows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reliable storage of N×analog values with reduced sigma in threshold voltage and drain current distributions, enhancing the performance of non-volatile memory devices for analog processing and neuromorphic computing applications.
Implementation Method 1
utilizing angled lightly doped drain implants and optimized oxide-nitride-oxide layers to minimize gate-induced drain leakage
Implementation Method 2
utilizing angled lightly doped drain implants and optimized oxide-nitride-oxide layers to minimize gate-induced drain leakage
Data Source
AI summary
A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N×analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.