Multi-gate Transistor Fabrication via Epitaxial Stack Segmentation
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistor features around nanowires in semiconductor manufacturing is challenging due to increased complexity and the need for improved gate control and reduced short-channel effects in advanced semiconductor devices.
Innovation Solution
A method for fabricating multi-gate devices involves applying an anti-punch through implant, forming an epitaxial stack, creating fin elements, and performing oxidation to establish an isolation region, followed by shallow trench isolation and the formation of a gate stack, which includes forming source/drain features and a spacer layer to enhance channel control and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scaling methods are used to reduce device dimensions, then production efficiency improves and costs decrease, but manufacturing complexity increases
Solution Approach 1:
The patent segments the channel region into multiple nanowires and surrounds each with a gate structure, creating a modular multi-gate device architecture. This segmentation allows for better control of short-channel effects while maintaining scalability in manufacturing processes.
Solution Approach 2:
The patent transitions from planar 2D gate control to 3D gate-all-around control, where the gate structure extends around the channel on multiple sides. This dimensional change provides superior electrostatic control and reduces short-channel effects without requiring further lateral scaling.
2Adaptability or versatility
If device dimensions are scaled down, then more functions can be integrated, but gate control deteriorates and short-channel effects increase
Solution Approach 1:
The gate structure extends around the channel region in three dimensions, providing gate-all-around control. This 3D configuration enhances electrostatic control over the channel, effectively suppressing short-channel effects even as device dimensions are scaled down to enable higher integration.
Solution Approach 2:
The gate structure is nested around the channel region, with the gate wrapping completely around the channel in a concentric configuration. This nested arrangement maximizes gate control efficiency and provides uniform electrostatic control from all directions.
3Reliability
If multi-gate device structures are implemented, then gate control improves and short-channel effects reduce, but fabrication complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming sacrificial nanowire structures, depositing gate materials around them, and selectively removing the sacrificial material. This segmentation simplifies the overall fabrication complexity by breaking down the complex multi-gate structure creation into manageable sequential steps.
Solution Approach 2:
Sacrificial nanowire structures are used as intermediary elements during fabrication. These temporary structures serve as templates for gate deposition and are later removed, simplifying the creation of the gate-all-around configuration without requiring direct complex 3D patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of multi-gate transistors with improved gate control and reduced short-channel effects, supporting the development of high-performance, low-power integrated circuits by effectively scaling semiconductor devices while maintaining gate control.
Implementation Method 1
applying an anti-punch through implant
Implementation Method 2
performing oxidation to establish an isolation region
Data Source
AI summary
A method of semiconductor device fabrication is described that includes forming a first fin extending from a substrate. The first fin has a source/drain region and a channel region and the first fin is formed of a first stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition. The method also includes removing the second epitaxial layers from the source/drain region of the first fin to form first gaps, covering a portion of the first epitaxial layers with a dielectric layer and filling the first gaps with the dielectric material and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a first source/drain feature while the dielectric material fills the first gaps.