Split Rail Standard Cell Library for 10 nm IR-Drop Mitigation
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Solution Overview
Problem
Standard power rail designs are insufficient for smaller process technologies, such as 10 nm, leading to issues with IR-drop and electromigration, which affect the performance and reliability of ASICs, particularly in high-frequency designs.
Innovation Solution
The implementation of multiple split power rail standard cell library architectures, where two sets of power rails, one for p-type MOS and one for n-type MOS, are used to provide distinct voltages, each set being interior to the cell boundary and extending across the MOS device, improving voltage distribution and reducing IR-drop and electromigration effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard power rail designs are used in smaller process technologies (e.g., 10 nm), then device integration is achieved, but IR-drop and electromigration issues occur that degrade performance and reliability
Solution Approach 1:
The power rail system is divided into multiple separate rails (at least two VDD rails and two VSS rails) instead of using a single shared power rail. Each rail is independently routed to serve specific transistor types (pMOS or nMOS), segmenting the power distribution network to reduce current density and mitigate IR-drop and electromigration effects in advanced 10 nm process technologies
Solution Approach 2:
Different power rail configurations are provided for different transistor types within the same cell. pMOS transistors receive power from dedicated VDD rails while nMOS transistors receive power from dedicated VSS rails, creating locally optimized power delivery paths that reduce harmful electrical effects specific to each transistor type's operating characteristics
2Device complexity
If shared power rails are used, then device complexity is reduced, but the power rail width must be increased to support IR-drop and electromigration requirements
Solution Approach 1:
Instead of using a single wide shared power rail, the system employs multiple narrower separate power rails (at least two VDD rails and two VSS rails). This segmentation allows each individual rail to have reduced width while collectively providing sufficient power distribution capacity, thereby reducing the maximum width required for any single power rail structure
3Object-affected harmful factors
If multiple split power rails are implemented, then IR-drop and electromigration are reduced, but device complexity increases
Solution Approach 1:
The power distribution network is segmented into multiple independent rails with dedicated routing paths for different transistor types. This segmentation reduces current density on each individual rail, thereby reducing IR-drop and electromigration effects, while the modular nature of the segmented architecture allows for systematic implementation that manages complexity
Solution Approach 2:
Multiple power rails are configured to maintain consistent voltage levels across different regions of the device. By providing separate VDD and VSS rails with proper connectivity and spacing, the design ensures equipotential conditions are maintained throughout the cell, reducing voltage drops while managing the complexity through standardized rail configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the performance and reliability of ASICs by reducing voltage drop and electromigration issues, supporting more efficient power delivery and maintaining performance across smaller process technologies.
Implementation Method 1
a first set of power rails and a second set of power rails. The first set of power rails extends in a first direction across the MOS device. The first set of power rails includes at least two power rails for providing a first voltage to the MOS device
Implementation Method 2
The second set of power rails extends in the first direction across the MOS device. The second set of power rails includes at least two power rails for providing a second voltage to the MOS device
Data Source
AI summary
A MOS device includes first and second sets of power rails. The first set of power rails extends across the MOS device and includes at least two power rails for providing a first voltage to the MOS device. The first set of power rails is interior to an edge of a cell boundary in the MOS device. At least one power rail of the first set of power rails extends over a pMOS active region of the MOS device. The second set of power rails extends across the MOS device and includes at least two power rails for providing a second voltage to the MOS device. The second set of power rails is interior to an edge of the cell boundary in the MOS device. At least one power rail of the second set of power rails extends over an nMOS active region of the MOS device.