Gate Electrode Corner Radius Reduction for Peripheral Circuit Area Shrinkage
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Solution Overview
Problem
The shrinking of field-effect transistors in peripheral circuit areas of nonvolatile semiconductor memory devices is hindered by the rounding of gate electrode corners due to photolithography and reactive ion etching, which affects transistor characteristics and makes it difficult to reduce the peripheral circuit area effectively.
Innovation Solution
The implementation of a gate electrode design with a radius of curvature less than 85 nm, achieved through two-time etching processes, where the gate electrode extends in the channel width direction and is divided into portions corresponding to element regions, with end and corner portions projecting onto the element isolation region, reducing the space between transistors and thus shrinking the peripheral circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory cell transistor is shrunk using sidewall processing technique, then the storage capacity is increased, but the peripheral circuit area cannot be effectively reduced due to gate electrode corner rounding
Solution Approach 1:
The gate electrode is divided into multiple segments along the channel width direction, with each segment corresponding to a specific element region. This segmentation allows independent optimization of each gate electrode portion, enabling the corner portions to be positioned on the element isolation region while maintaining proper transistor operation in each element region.
Solution Approach 2:
Different portions of the gate electrode are designed with different properties: the end portions and corner portions are positioned on the element isolation region to reduce overall transistor size and enable peripheral circuit area reduction, while the central portions spanning the element regions maintain appropriate dimensions to ensure proper transistor characteristics and operation.
2Area of stationary object
If the gate electrode corner radius of curvature is reduced to shrink transistor size, then the peripheral circuit area is reduced, but the transistor characteristics are affected by excessive rounding
Solution Approach 1:
The gate electrode is segmented such that corner portions with reduced radius of curvature (less than 85 nm) are isolated on the element isolation region, while the central portions maintaining proper dimensions remain positioned over the element regions. This ensures transistor characteristics are preserved while achieving size reduction.
Solution Approach 2:
The element isolation region serves as an intermediary structure that accommodates the gate electrode corner portions with reduced radius of curvature. By positioning these rounded corners on the isolation region rather than directly over element regions, the negative effects of rounding on transistor characteristics are mitigated while still achieving the desired size reduction.
Data Source
AI summary
A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.