Stacked SRAM Inverter Layout With Backside PDN Power Rails
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Solution Overview
Problem
Current integrated circuit devices face challenges in increasing integration density and simplifying the back-end-of-line (BEOL) portion of device fabrication, particularly in the configuration of power distribution networks and interconnections between transistors.
Innovation Solution
The proposed solution involves a stacked transistor structure with upper and lower transistors forming an inverter, where the transistors are stacked to reduce area and simplify interconnections, and a power distribution network (PDN) structure with linearly arranged power rails on the backside of the substrate, connected through power contacts and shared contacts to enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar transistor layouts are used, then fabrication is simpler, but integration density is lower
Solution Approach 1:
The patent transitions from planar 2D transistor layouts to a 3D stacked configuration where upper transistors are positioned vertically above lower transistors. This dimensional change allows multiple transistor layers to occupy the same footprint area, thereby increasing integration density without proportionally increasing the device footprint.
Solution Approach 2:
The patent implements a nested structure where upper transistors are embedded within the vertical space above lower transistors. The source/drain regions of upper transistors are positioned to overlap with and nest above the source/drain regions of lower transistors, creating a compact stacked arrangement that maximizes space utilization.
2Reliability
If complex power distribution networks are used, then power delivery is more robust, but BEOL fabrication becomes more difficult
Solution Approach 1:
The patent segments the power distribution network into separate upper and lower power rails that are independently formed. The upper power rail is formed in the upper interlayer dielectric, while the lower power rail is formed in the lower interlayer dielectric. This segmentation allows each power rail to be fabricated independently through separate via holes, simplifying the BEOL process while providing robust power delivery to both upper and lower transistor layers.
Solution Approach 2:
The patent introduces intermediate connection structures (via holes and contact plugs) that mediate the electrical connection between the upper and lower power rails and the respective transistor layers. These intermediary elements facilitate independent formation and connection of power distribution paths, reducing fabrication complexity while maintaining reliable power delivery.
3Area of moving object
If stacked transistor structures are used, then area is reduced, but interconnection complexity increases
Solution Approach 1:
The patent merges the interconnection paths by forming source/drain connectors that combine the source/drain regions of upper and lower transistors into unified connection points. The upper source/drain regions are connected to corresponding lower source/drain regions through vertical vias, creating merged interconnection structures that reduce the number of separate interconnections needed while maintaining compact area.
Data Source
AI summary
Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a static random access memory (SRAM) unit. The SRAM unit may include a first inverter on a substrate and a power distribution network (PDN) structure including a first power rail and a second power rail. The substrate may extend between the first inverter and the PDN structure. The first inverter may include a first upper transistor including a first upper source/drain region, a first lower transistor between the substrate and the first upper transistor and including a first lower source/drain region, a first power contact extending through the substrate and electrically connecting the first upper source/drain region to the first power rail, and a second power contact extending through the substrate and electrically connecting the first lower source/drain region to the second power rail.