Segmented Source/Drain Layout for Dense Reliable Semiconductor Cells
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Solution Overview
Problem
There is a need for semiconductor devices with high integration density and improved reliability to meet increasing demands for high performance and multiple functions, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor device design featuring a channel region between source/drain patterns with a gate electrode on the bottom surface and an upper interconnection line on the insulating layer, along with specific configurations of source/drain patterns and active regions, enhances integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the structural complexity and integration density are increased to satisfy high performance and multiple functions, then the device capability is improved, but the manufacturing difficulty and reliability risks increase
Solution Approach 1:
The source/drain structure is divided into multiple segments including deep source/drain regions, shallow source/drain regions, and offset source/drain regions. This segmentation allows each region to be optimized independently for different functions (carrier transport, stress application, electrical contact) while maintaining overall device reliability despite increased integration density
Solution Approach 2:
The patent implements nested source/drain structures where shallow source/drain regions are positioned within or adjacent to deep source/drain regions, and offset source/drain regions are positioned at different vertical levels. This nesting approach maximizes integration density by utilizing three-dimensional space efficiently while maintaining proper electrical and mechanical functionality
2Adaptability or versatility
If the structural complexity is increased to achieve multiple functions, then the device functionality is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The gate electrode is formed first as a reference structure, followed by the formation of deep source/drain regions, then shallow source/drain regions, and finally offset source/drain regions. Each subsequent structure is positioned relative to previously formed structures, using them as alignment references to maintain manufacturing precision despite the complexity of multiple functions
Solution Approach 2:
Different regions of the source/drain structure are assigned different properties and functions: deep source/drain regions for carrier transport, shallow source/drain regions for stress application, and offset source/drain regions for electrical contact. This local differentiation allows each region to be optimized for its specific function while maintaining overall manufacturing feasibility
Data Source
AI summary
A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.