CMOS Image Sensor Charge Transfer With V-NW FD Noise Suppression

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Solution Overview

Problem

The capacitance of the PN junction in CMOS image sensors contributes significantly to read noise, limiting noise reduction and allowing leakage currents that generate dark current, which is a common issue across various CIS structures.

Innovation Solution

A solid-state image pickup apparatus utilizing V-NW transistors with a wiring layer having no PN junction, reducing capacitance and eliminating leakage currents, and featuring an impurity-containing insulating film to pin the Fermi level, thereby suppressing read noise and dark current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a PN junction is used to form the floating diffusion layer for charge accumulation, then the charge can be accumulated effectively, but the capacitance of the PN junction contributes significantly to read noise and leakage currents generate dark current

Engineering Contradiction:
Improvecharge accumulation capabilityVSAvoidread noise and dark current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and removes the PN junction structure from the charge accumulation section. Instead of using a traditional floating diffusion layer formed by PN junction, the invention uses a simple wiring layer (metal layer) to accumulate charges. This extraction of the harmful PN junction element eliminates the source of read noise and dark current while preserving the charge accumulation function.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the material parameter of the accumulation section from semiconductor (PN junction) to metal (wiring layer). This parameter change fundamentally alters the electrical characteristics, eliminating junction capacitance and leakage currents associated with PN junctions, thereby reducing read noise and dark current.

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If the capacitance of the PN junction is reduced to suppress read noise, then read noise may be reduced, but the reduction is limited because the FD is realized by forming the PN junction on the Si substrate

Engineering Contradiction:
Improveread noiseVSAvoidcapacitance reduction limit
Core Design Contradiction:
Object-generated harmful factorsVSManufacturing precision

Solution Approach 1:

The patent completely removes the PN junction structure from the accumulation section, replacing it with a metal wiring layer. This extraction eliminates junction capacitance entirely rather than attempting to reduce it, thereby overcoming the manufacturing precision limits associated with minimizing PN junction capacitance.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If a planar transistor structure is used, then the device can be manufactured with existing processes, but the capacitance around the floating diffusion layer causes read noise

Engineering Contradiction:
ImprovemanufacturabilityVSAvoidread noise
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the harmful capacitance element (PN junction floating diffusion) from the planar transistor structure and replaces it with a metal wiring layer. This maintains compatibility with existing planar manufacturing processes while eliminating the read noise problem caused by junction capacitance.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively minimizes read noise and improves light sensitivity by reducing capacitance and eliminating dark current, enhancing the area efficiency of the photoelectric conversion section.

Implementation Method 1

an impurity-containing insulating film to pin the Fermi level

Methodology Applied
Scientific EffectFermi level pinning:

Implementation Method 2

an impurity-containing insulating film formed between the photoelectric conversion section and a gate of the V-NW transistor forming the transfer section

Methodology Applied
Scientific EffectImpurity diffusion: Diffusion

Data Source

PatentUS11804500B2Solid-state image pickup apparatus and electronic equipment
Publication Date: 2023.10.31 SONY SEMICON SOLUTIONS CORP
  • US11804500B2 patent drawing
  • US11804500B2 patent drawing
  • US11804500B2 patent drawing

AI summary

A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.