Variable Gate Spacer Layout for SRAM Short Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional designs for high-density SRAM bitcells in advanced technology nodes, such as 5 nm and beyond, suffer from high defect rates and yield loss due to gate-to-source/drain (S/D) shorts, which are difficult to eliminate and result in reliability issues that exceed the stringent requirements of demanding applications like ADAS products.
Innovation Solution
The implementation of a semiconductor device with varying gate spacer structures, where SRAM transistors have a thicker first gate spacer structure, logic nominal transistors have a similar second gate spacer structure, and logic gate-biased transistors have a thinner third gate spacer structure, all maintaining the same contacted poly pitch (CPP), to eliminate gate-to-S/D contact shorts without increasing chip area or disrupting logic gate-biased device designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gate-to-source/drain space is shrunk to increase design density, then the design density is improved, but gate-to-source/drain contact shorts occur increasing defect rates
Solution Approach 1:
The patent applies different gate spacer thicknesses to different transistor types within the same circuit. SRAM transistors receive a first gate spacer thickness while logic transistors receive a second gate spacer thickness. This local differentiation allows the SRAM circuits to maintain higher design density with smaller gate-to-source/drain spacing, while logic circuits can use larger spacing to prevent shorts, thereby resolving the contradiction between density and reliability.
2Reliability
If a thicker gate spacer structure is used to prevent gate-to-source/drain shorts, then reliability is improved, but design density decreases
Solution Approach 1:
The invention implements local quality by assigning different gate spacer thicknesses to different functional blocks. Logic transistors use a thicker gate spacer (second thickness) to prevent contact shorts and ensure reliability, while SRAM transistors use a thinner gate spacer (first thickness) to maintain high design density. This selective approach prevents the reliability improvement from causing overall density degradation.
3Ease of manufacture
If uniform gate spacer structures are used across all transistors, then manufacturing is simplified, but both SRAM density and logic reliability cannot be optimized simultaneously
Solution Approach 1:
The patent resolves the manufacturing complexity issue by forming the first and second gate spacers as separate distinct structures rather than attempting to create variable thicknesses in a single uniform spacer layer. This approach maintains relative manufacturing simplicity while enabling different spacer thicknesses for different transistor types, thereby optimizing both SRAM density and logic reliability simultaneously.
Data Source
AI summary
Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include one or more static random-access memory (SRAM) transistors, each including a first gate spacer structure; one or more logic nominal transistors, each including a second gate spacer structure; and one or more logic gate-biased transistors, each including a third gate spacer structure, where the third gate spacer structure is thinner than the first gate spacer structure and where the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate-biased transistors each have a same contacted poly pitch (CPP).