Backside Trench Capacitor Wiring for Low-Noise Power Delivery
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Solution Overview
Problem
As semiconductor devices become increasingly complex and integrated, they face challenges in maintaining high reliability and performance due to voltage drop in power delivery networks, particularly as wiring patterns and via patterns decrease in size, leading to inefficiencies in power supply and increased noise.
Innovation Solution
The semiconductor device incorporates a trench capacitor that fills a deep trench in the substrate, acting as a high-performance capacitor in the power delivery network, and a back wiring structure on the substrate's second face to connect through-vias and electronic elements, reducing voltage drop and enhancing power performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If wiring patterns and via patterns are decreased in size to increase integration, then device complexity is reduced and area is minimized, but voltage drop increases and power delivery performance deteriorates
Solution Approach 1:
The patent introduces a back wiring structure on the rear surface of the substrate, transitioning from a planar two-dimensional wiring layout to a three-dimensional configuration that utilizes both front and back surfaces. This dimensional expansion allows power delivery paths to be established in the vertical dimension (through substrate thickness), reducing current density and voltage drop in the planar direction while maintaining compact device area.
Solution Approach 2:
The power delivery network is segmented into multiple independent pathways: front wiring patterns, back wiring patterns, and through-substrate vias. This segmentation distributes the power delivery load across multiple parallel paths, reducing current density in each individual conductor and thereby minimizing voltage drop and resistive losses.
2Area of stationary object
If wiring patterns are decreased in size to increase integration, then area is minimized, but power supply noise increases
Solution Approach 1:
The power delivery network is divided into multiple segmented pathways including front wiring, back wiring, and through-substrate connections. This segmentation distributes high-frequency current across multiple parallel paths, reducing current density and thereby minimizing electromagnetic radiation and power supply noise in each individual conductor while maintaining compact area.
Solution Approach 2:
By establishing power delivery paths on both front and back surfaces of the substrate and connecting them through vias, the patent creates a three-dimensional power network that increases the effective surface area for current distribution. This dimensional expansion reduces current density and electromagnetic interference, thereby reducing power supply noise while maintaining small device footprint.
3Productivity
If device integration is increased to improve performance, then functionality is enhanced, but voltage drop in power delivery network increases
Solution Approach 1:
The patent utilizes the third dimension (substrate thickness) by implementing a back wiring structure and through-substrate vias, creating a three-dimensional power delivery network. This allows power to be delivered to highly integrated circuits through multiple parallel paths in the vertical dimension, reducing current density and voltage drop even as device integration and performance increase.
Solution Approach 2:
The power delivery system is segmented into multiple independent pathways (front wiring, back wiring, through-vias) that can simultaneously serve highly integrated circuit blocks. This segmentation enables scalable power delivery to high-performance devices by distributing load across multiple paths, preventing voltage drop from increasing linearly with integration level.
Data Source
AI summary
A semiconductor device includes: a substrate including a first face, on which an active area is formed, and a second face opposite to the first face; an electronic element formed on the active area; a front wiring structure disposed on the first face of the substrate and connected to the electronic element; a trench capacitor filling at least a portion of a back trench extending into the substrate from the second face of the substrate; a back wiring structure disposed on the second face of the substrate and connected to the trench capacitor; and a through-via extending through the substrate to electrically connect the electronic element and the back wiring structure to each other.