FinFET Source/Drain Epitaxy to Prevent Region Merging
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Solution Overview
Problem
As semiconductor devices, such as FinFETs, continue to shrink in size to increase integration density, fully strained channel architectures face challenges in preventing the merging of adjacent source/drain regions, which affects device performance and critical dimension uniformity.
Innovation Solution
A multi-cycle epitaxial growth process involving repeated deposition and etching (dep-etch) is used to restrain horizontal growth of source/drain regions, increasing their height and volume, thereby preventing merging and improving critical dimension uniformity and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fully strained channel architecture is used to improve FinFET performance, then device performance is improved, but adjacent source/drain regions merge together
Solution Approach 1:
The source/drain region formation is divided into multiple epitaxial growth cycles with intermediate etching steps. Each cycle grows a portion of the source/drain region, then etching removes excess material before the next growth cycle begins. This segmentation prevents merging of adjacent source/drain regions while achieving the desired height and strain.
Solution Approach 2:
The patent employs periodic epitaxial growth and etching cycles to form source/drain regions. The process alternates between depositing epitaxial material to increase source/drain height and performing selective etching to prevent lateral merging. This periodic action maintains critical dimension uniformity while achieving the required strain for high performance.
2Reliability
If source/drain regions are grown larger in volume to provide more contact area, then contact resistance is reduced, but adjacent regions merge together
Solution Approach 1:
The source/drain region growth is segmented into multiple cycles, where each cycle contributes to the overall volume without causing merging. The intermediate etching steps between cycles remove excess lateral material, allowing the source/drain regions to achieve sufficient volume for low contact resistance while maintaining separation between adjacent regions.
Solution Approach 2:
The patent focuses growth on the vertical dimension through multiple epitaxial cycles, increasing source/drain height to provide adequate contact volume. By controlling lateral growth through selective etching, the process achieves the desired volume increase primarily in the vertical dimension rather than allowing uncontrolled lateral expansion that would cause merging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process enhances device performance by providing a larger volume for metal contact, reducing contact resistance and improving the integration density of semiconductor components.
Implementation Method 1
Selective epitaxial growth is performed in the first and second recesses to form the first and second source/drain regions, respectively
Implementation Method 2
a strained channel region between the gate electrode and the source/drain regions
Data Source
AI summary
A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.