FinFET Replacement Gate Division Using a Dielectric Separation Wall
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating fin field effect transistors (Fin FETs) with high aspect ratios, where the existing gate-replacement technologies struggle to achieve precise control over the gate structure and fin spacing, leading to inefficiencies in device performance and reliability.
Innovation Solution
The introduction of a dielectric separation wall made of materials like SiCN, SiOCN, or metal oxides (HfO2, ZrO2, Al2O3) between fin structures, which allows for the formation of a dummy gate structure that is later replaced by a metal gate, enabling precise control over fin spacing and gate structure dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-replacement technology is used to form metal gate structures in Fin FETs, then device performance and reliability are improved, but control over gate structure dimensions and fin spacing becomes imprecise
Solution Approach 1:
The gate structure formation process is segmented into distinct stages: forming the dummy gate structure separately, forming the metal gate structure separately, and using a dielectric separation wall to divide them. This segmentation allows independent optimization and precise control of each component's dimensions and positioning.
Solution Approach 2:
A dielectric separation wall is introduced as an intermediary element between the dummy gate structure and the metal gate structure. This separation wall acts as a spacer and positioning reference, enabling precise control over the spacing and dimensions of the gate structures while maintaining the benefits of gate-replacement technology.
2Productivity
If high aspect ratio fins are used to increase device density, then productivity is improved, but manufacturing precision and control over fin spacing deteriorate
Solution Approach 1:
The dielectric separation wall is formed in advance before the metal gate structure. This preliminary action establishes precise spacing references and positioning guides that control the subsequent formation of high aspect ratio fins and metal gate structures, ensuring accurate fin spacing even at high device densities.
Solution Approach 2:
The dielectric separation wall serves as an intermediary spacer that physically defines and controls the spacing between fins. By using this intermediate structure with controlled thickness, precise fin spacing is achieved while maintaining high aspect ratios and increasing device density.
3Manufacturing precision
If dielectric separation wall is introduced between fin structures, then manufacturing precision of gate structure is improved, but device complexity increases
Solution Approach 1:
The dielectric separation wall performs multiple functions simultaneously: it acts as a spacer for precise spacing control, a positioning reference for gate structure alignment, and a structural divider between dummy and metal gate regions. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.