SOI Resistance Element Layout for Higher Resistance in Less Area
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Solution Overview
Problem
The challenge is to increase the resistance value of a resistance element in a semiconductor device without increasing the device's area, which is essential for miniaturization, as higher resistance values typically require larger areas, hindering device miniaturization.
Innovation Solution
The semiconductor device incorporates a resistance element with a semiconductor layer and epitaxial semiconductor portions on a support substrate, featuring specific impurity concentration regions and a thin element portion without epitaxial growth, allowing for increased resistance without area expansion. This design includes regions with varying impurity concentrations and a thin current path to enhance resistance without increasing the device's footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the resistance value of the resistance element is increased, then the resistance performance is improved, but the area required for arranging the resistance element increases
Solution Approach 1:
The patent applies local quality by creating regions with different impurity concentrations within the resistance element. Specifically, it forms a low-concentration region adjacent to the high-concentration region, and a medium-concentration region on top of the low-concentration region. This spatial variation in impurity concentration allows different parts of the resistance element to contribute differently to the overall resistance, achieving high resistance values in a compact area.
Solution Approach 2:
The patent transitions from a two-dimensional planar resistance structure to a three-dimensional layered structure by forming epitaxial semiconductor layers at different heights. The resistance element includes a semiconductor layer on the support substrate, with first and second epitaxial semiconductor portions formed at different vertical levels, creating a stacked configuration that increases resistance without proportionally increasing the planar area.
2Reliability
If the area of the semiconductor device is increased to accommodate higher resistance elements, then the resistance value can be increased, but the miniaturization of the semiconductor device is hindered
Solution Approach 1:
The patent implements nesting by placing the first epitaxial semiconductor portion inside or adjacent to the second epitaxial semiconductor portion in a vertical stacking arrangement. The low-concentration region and medium-concentration region are nested within the same planar footprint, allowing the resistance element to achieve high resistance values without increasing the overall device area, thus supporting miniaturization.
3Reliability
If a uniform impurity concentration is used throughout the resistance element, then the manufacturing process is simplified, but the resistance value cannot be sufficiently increased without increasing area
Solution Approach 1:
The patent segments the resistance element into distinct regions with different impurity concentrations: a high-concentration region, a low-concentration region adjacent to it, and a medium-concentration region on the low-concentration region. This segmentation allows each region to contribute differently to the overall resistance, achieving high resistance values in a compact area while maintaining manufacturability through standardized epitaxial growth processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the resistance value of the resistance element while maintaining a compact device size, improving miniaturization capabilities and reducing manufacturing complexity and costs.
Implementation Method 1
a first epitaxial semiconductor portion formed on the semiconductor layer located in the first region; and a second epitaxial semiconductor portion formed on the semiconductor layer located in the first region so as to be spaced apart from each other
Data Source
AI summary
A resistance element is comprised of a first semiconductor layer of an SOI substrate and a second semiconductor layer formed on the first semiconductor layer. The second semiconductor layer has first and second semiconductor portions spaced apart from each other. The first semiconductor layer has a first region on which the first semiconductor portion is formed, a second region on which the second semiconductor portion is formed, and a third region on which no epitaxial semiconductor layer is formed. Each of the first region and the second region further has a low concentration region located next to the third region. An impurity concentration of the low concentration region is lower than an impurity concentration of the third region. Each semiconductor portion has a middle concentration region located on the low concentration region. An impurity concentration of the middle concentration region is higher than that of the low concentration region.