FinFET Spacer Profile for Lower Gate-to-Drain Capacitance
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in reducing the volume and cross-sectional area of source/drain regions, leading to increased gate-to-drain capacitance and RC delay, which hinders device performance.
Innovation Solution
The formation of epitaxial source/drain regions with reduced volume and cross-sectional area is achieved by depositing a spacer material over fins and etching it to create higher portions between adjacent fins, allowing lateral growth from a higher point, thereby reducing the merged source/drain region's cross-sectional area and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If source/drain region volume is reduced to improve integration density, then device miniaturization is achieved, but gate-to-drain capacitance increases and RC delay worsens
Solution Approach 1:
The patent applies dimensionality change by forming epitaxial source/drain regions that grow laterally from a higher elevation point rather than from the substrate level. This vertical displacement of the growth initiation point reduces the horizontal spread of the source/drain regions, thereby reducing their cross-sectional area and volume while minimizing their overlap with the gate electrode, which reduces gate-to-drain capacitance.
Solution Approach 2:
The patent employs local quality by creating non-uniform spacer material heights between adjacent fins, with higher portions positioned strategically to control where lateral epitaxial growth occurs. This localized variation in spacer height allows precise control over the source/drain region formation, enabling reduced volume while maintaining electrical performance by preventing excessive capacitance formation.
2Productivity
If source/drain region cross-sectional area is reduced to improve device speed, then RC delay is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by depositing and patterning spacer material before the epitaxial growth of source/drain regions. The spacer material is formed with predetermined height variations that pre-establish the template for where lateral growth will occur. This preliminary structuring simplifies the subsequent epitaxial growth process, as the growth automatically follows the spacer geometry, reducing the need for complex post-growth processing steps.
Solution Approach 2:
The spacer material serves as an intermediary structure that mediates between the fin structure and the epitaxial source/drain regions. By using the spacer as a template and growth barrier, the patent simplifies the control of source/drain region geometry. The intermediary spacer material enables precise control of the epitaxial growth initiation point and lateral extent, achieving reduced cross-sectional area without requiring complex direct patterning of the source/drain regions themselves.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced gate-to-drain capacitance, faster switching speed, and improved device performance by minimizing RC delay and boosting speed.
Implementation Method 1
portions of the epitaxial source/drain regions within the inner regions are separated from the first remaining portions of the spacer layer by a bottom inner surface of the epitaxial source/drain regions
Data Source
AI summary
A method includes forming a gate structure over fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; depositing a spacer layer over the gate structure and over the fins, wherein the spacer layer fills the regions extending between pairs of adjacent fins; performing a first etch on the spacer layer, wherein after performing the first etch, first remaining portions of the spacer layer that are within inner regions extending between pairs of adjacent fins have a first thickness and second remaining portions of the spacer layer that are not within the inner regions have a second thickness less than the first thickness; and forming an epitaxial source/drain region adjacent the gate structure and extending over the fins, wherein portions of the epitaxial source/drain region within the inner regions are separated from the first remaining portions of the spacer layer.