Low-Leakage TFTs via Composite Semiconductor Layers

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Solution Overview

Problem

In AMOLED display manufacturing, the non-uniformity of low-temperature polysilicon semiconductors leads to threshold voltage drifts, causing abnormal light emission due to high leakage currents in thin-film transistors, which current pixel compensation circuits struggle to address effectively.

Innovation Solution

The implementation of a display panel driving circuit with low-leakage current thin-film transistors, comprising a semiconductor layer with low-temperature polysilicon and another layer with lower carrier mobility, such as metal oxide or amorphous silicon, to reduce leakage currents and prevent abnormal light emission, eliminating the need for TFT-aging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If TFT-aging is applied to reduce leakage current, then leakage current is reduced, but the process cannot age TFTs in non-AA areas such as GOA area

Engineering Contradiction:

Improveleakage current reductionVSAvoidapplicability to different areas

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent changes the material parameter of the semiconductor layer from conventional LTPS to OTS (oxide semiconductor), which fundamentally alters the electrical characteristics to achieve low leakage current without requiring aging processes. This material parameter change enables universal application across different display panel areas including both AA and GOA regions.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite structure with multiple semiconductor layers having different materials and properties. The OTS layer provides low leakage current characteristics while being compatible with standard manufacturing processes, creating a composite solution that combines the benefits of material innovation with process compatibility.

Inventive Principle:

Principle #40Composite materials

2Speed

If LTPS is used for array substrate, then high carrier mobility is achieved, but uniformity of large-area polysilicon semiconductors is poor causing threshold voltage drifts

Engineering Contradiction:

Improvecarrier mobilityVSAvoiduniformity of polysilicon semiconductor

Core Design Contradiction:

SpeedVSManufacturing precision

Solution Approach 1:

The patent transitions from LTPS material to OTS material, changing the fundamental semiconductor parameter. OTS provides both high carrier mobility and superior uniformity across large areas, eliminating the threshold voltage drift problem while maintaining high-speed performance. This material parameter change resolves the contradiction between speed and manufacturing precision.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces the conventional LTPS crystallization process with an OTS formation process that does not rely on high-temperature crystallization. This substitution of the semiconductor material system eliminates the uniformity issues inherent in large-area LTPS fabrication while preserving the desired electrical performance.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11482546B2Method of fabricating array substrate

Publication Date: 2022.10.25 WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO LTD

AI summary

A display panel driving circuit, an array substrate, and a method of fabricating the array substrate are provided. The display panel driving circuit includes a plurality of transistors. The transistors include a low leakage current thin-film transistor including a semiconductor layer. The semiconductor layer includes a first semiconductor layer and a second semiconductor layer disposed on the first semiconductor layer. A material of the first semiconductor layer or the second semiconductor is low-temperature polysilicon, and a material of the other has a carrier mobility less than a carrier mobility of the low-temperature polysilicon.