Recessed MV MOSFET Gate Structure for Planarization Control
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Solution Overview
Problem
The integration of manufacturing multiple MOSFETs with different threshold voltages on a single wafer is challenging due to the varying thicknesses of gate dielectric layers, leading to issues with gate height control and planarization processes, where medium voltage MOSFETs often have their gate completely removed during planarization, affecting device performance and efficiency.
Innovation Solution
A new gate structure is introduced with a recess in the semiconductor substrate, where the gate dielectric layer is formed within the recess, and sidewall spacers are used to protect it from source/drain regions and silicide layers, allowing for better height control and simultaneous processing of MOSFETs with varying gate dielectric layer thicknesses, ensuring uniformity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planarization is performed to flatten the wafer surface, then manufacturing efficiency is improved, but the MV gate may be incompletely removed or the gate dielectric layer may be degraded
Solution Approach 1:
The patent applies local quality by creating a recessed structure specifically for the MV gate region, allowing different areas of the wafer to have different topographies. The MV gate is formed in a recess while the LV gate remains at the surface level, enabling selective planarization that removes the MV gate completely while preserving the LV gate and protecting the gate dielectric layer from degradation
Solution Approach 2:
The patent segments the gate structures by spatially separating MV and LV MOSFET regions on the wafer. The MV MOSFETs are formed in recessed areas while LV MOSFETs are formed at the surface level, allowing independent processing and planarization for each type without mutual interference
2Adaptability or versatility
If MV and LV MOSFETs are integrated on a single wafer, then device versatility is improved, but manufacturing complexity increases due to varying gate dielectric layer thicknesses
Solution Approach 1:
The patent implements local quality by providing different structural environments for MV and LV MOSFETs on the same wafer. MV MOSFETs are formed in recessed regions with thicker gate dielectric layers, while LV MOSFETs are formed at the surface with thinner gate dielectric layers, allowing both device types to be manufactured simultaneously with their respective optimal parameters
Solution Approach 2:
The patent introduces a vertical dimension by creating recessed structures in the substrate. This vertical segmentation allows MV and LV MOSFETs to coexist on a single wafer plane by utilizing different depth levels, effectively adding a third dimension (depth) to the otherwise two-dimensional integration problem
3Reliability
If the gate dielectric layer thickness is increased for MV devices, then voltage handling capability is improved, but the gate height control becomes more difficult during processing
Solution Approach 1:
The patent applies preliminary action by forming the recessed structure before depositing the gate dielectric layer. This pre-formed recess provides a physical constraint that automatically limits the gate dielectric layer thickness for MV devices, ensuring consistent gate height and eliminating the need for complex thickness control during the deposition process
Data Source
AI summary
In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.