FinFET Backside Source/Drain Contact Layout for Low Parasitic Capacitance
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Solution Overview
Problem
The downscaling of integrated circuit (IC) devices requires high operating speed and accuracy, necessitating stable and optimized wiring structures within a reduced area, while existing technologies face challenges in minimizing parasitic capacitance and resistance in these compact designs.
Innovation Solution
The IC device incorporates a fin-type active region with a back side source/drain contact structure, including a contact space between fin portions, a device isolation film, and an etch stop layer, which ensures sufficient insulation and reduces resistance by aligning back and front side source/drain contacts without strict design rules, facilitating self-aligned etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the area of IC device is reduced for downscaling, then integration density is improved, but parasitic capacitance increases due to insufficient insulation distance
Solution Approach 1:
The patent utilizes the vertical dimension by forming back side source/drain contacts that extend through the substrate thickness direction. This allows contacts to reach source/drain regions without requiring lateral expansion, thereby maintaining reduced planar area while ensuring adequate insulation distances are preserved in the horizontal plane to minimize parasitic capacitance.
Solution Approach 2:
The device is segmented into front side and back side contact structures. Back side contacts are formed through openings in the substrate, separating the contact formation process into distinct stages and allowing independent optimization of contact positioning and insulation spacing to reduce parasitic effects.
2Speed
If wiring structures are optimized for high operating speed, then performance is improved, but resistance of power and signal wirings increases
Solution Approach 1:
Power and signal wirings are extended into the vertical dimension by forming back side contacts that penetrate through the substrate thickness. This three-dimensional wiring approach provides additional conduction paths and reduces lateral current density, thereby lowering resistance while maintaining high operating speed performance.
3Area of moving object
If back side source/drain contact structure is implemented, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The substrate thickness is preliminarily controlled within a specific range (50-150 nm) to enable self-aligned etching processes. This preliminary dimensioning allows subsequent back side contact formation to proceed automatically with proper alignment, reducing the need for complex alignment steps and simplifying manufacturing while achieving high integration density.
Solution Approach 2:
The etching process for forming back side contact openings utilizes self-alignment mechanisms where the etch depth is automatically controlled by the substrate thickness. This self-service approach eliminates the need for complex depth control systems and multiple alignment steps, reducing manufacturing complexity while maintaining precise contact positioning.
Data Source
AI summary
An integrated circuit device includes a fin-type active region including a first fin portion and a second fin portion apart from each other in a first lateral direction with a contact space therebetween, a first source/drain region on the fin-type active region at a position overlapping the contact space in a vertical direction, a gate line on the first fin portion, a device isolation film covering both sidewalls of each of the first and second fin portions and defining a width of the contact space, a back side source/drain contact electrically connected to the first source/drain region, filling the contact space, and having a sidewall facing each of the first and second fin portions and the device isolation film, and an etch stop layer contacting a top surface of each of the first and second fin portions between the first fin portion and the gate line.