FinFET Source/Drain Recess Shaping for Low-Parasitic Epitaxy
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing epitaxial source/drain structures for FinFETs due to the need for precise control of recess profiles and epitaxial growth, particularly in forming voids between the source/drain epitaxial layers and isolation insulating layers to reduce parasitic capacitance and improve device performance.
Innovation Solution
A method involving asymmetric pulsed-bias etching is used to form a W-shaped recess in the source/drain regions, allowing for the growth of a merged epitaxial source/drain structure with controlled volume and topography, which reduces parasitic capacitance and enhances device mobility by maintaining a fin mask layer on the isolation insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form recesses in source/drain regions, then the manufacturing process is simple, but the recess profile control precision is insufficient and void formation is difficult
Solution Approach 1:
The patent applies periodic pulsed bias voltage during plasma etching to achieve precise recess profile control. The pulsed bias voltage creates alternating high and low etching rates that enable formation of the desired W-shaped recess profile with controlled voids, resolving the contradiction between precision and process simplicity.
Solution Approach 2:
The patent changes the bias voltage parameter dynamically during the etching process by applying pulsed bias voltage with specific duty cycles and amplitudes. This parameter modulation allows precise control of the recess profile shape and void formation, achieving high manufacturing precision while managing process complexity through systematic parameter control.
2Manufacturing precision
If the fin mask layer is removed completely, then the device structure is simplified, but the epitaxial growth control and void formation are compromised
Solution Approach 1:
The patent applies local quality by selectively retaining the fin mask layer in specific regions where it serves as a template for void formation during epitaxial growth. The mask layer is not completely removed but preserved locally to define the void geometry, achieving precise epitaxial growth control while accepting increased structural complexity in exchange for manufacturing precision.
3Reliability
If the recess depth is increased to reduce parasitic capacitance, then the device performance improves, but the epitaxial layer contact area is reduced
Solution Approach 1:
The patent employs curved/W-shaped recess profiles instead of simple linear deep recesses. The W-shape geometry provides both sufficient depth for parasitic capacitance reduction and lateral extent for maintaining epitaxial layer contact area. The curved profile optimizes the trade-off between vertical depth and horizontal contact area, achieving both reliability improvement and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the epitaxial layer's contact area and mobility, reducing parasitic capacitance and enhancing the performance of FinFETs by optimizing the recess shape and epitaxial growth, thereby addressing the challenges of precise control and void formation in existing manufacturing processes.
Implementation Method 1
By a plasma etching process, a source/drain region of the fin structure is recessed to form a recess
Implementation Method 2
An epitaxial source/drain structure is formed over the recessed fin structures
Data Source
AI summary
In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.