Cascode Switching Module With Self-Powered Gate Driver

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Solution Overview

Problem

State-of-the-art cascode switching modules using GaN devices face issues with reliability degradation due to parasitic inductances and capacitance mismatch, leading to oscillations and increased power losses, and require external gate drivers that compromise Common Mode Transient Immunity (CMTI) performance and increase hardware complexity.

Innovation Solution

A cascode switching module that integrates a normally-on GaN HEMT with a normally-off MOSFET and an in-situ gate driver, powered by the GaN device, which minimizes parasitic inductances and noise, and includes a capacitor to store energy for the gate driver, reducing overshoots and power losses, and eliminates the need for external gate driver power supplies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large capacitor Cx is integrated into the MOSFET die to mitigate middle point voltage overshoot, then reliability degradation is reduced, but power losses increase and chip size increases

Engineering Contradiction:
ImproveGaN gate reliabilityVSAvoidpower loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent segments the capacitor function by placing it externally rather than integrating it into the MOSFET die. This separates the voltage mitigation function from the power switching function, allowing the capacitor to reduce overshoot without its energy being dissipated in the MOSFET channel during turn-on.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary circuit configuration where the capacitor Cx is connected through specific parasitic inductances (Lp1, Lp2) rather than being directly integrated. This intermediary placement allows the capacitor to mitigate voltage overshoot while avoiding direct energy dissipation in the MOSFET channel.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a bleeder resistor Rx is integrated into the MOSFET die to sink GaN leakage current, then unwanted cascode turn-on events are prevented, but efficiency is compromised

Engineering Contradiction:
Improvecascode stabilityVSAvoidefficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent extracts the bleeder resistor function from the MOSFET die by implementing it as an external circuit element. This removes the continuous power loss associated with integrated bleeder resistors while maintaining the ability to sink GaN leakage current and prevent unwanted turn-on events.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs periodic action by using the gate driver circuit to actively manage the GaN device state rather than continuous leakage sinking. The gate driver periodically reinforces the off-state of the GaN device, eliminating the need for continuous power dissipation through a bleeder resistor.

Inventive Principle:
Principle #19Periodic action

3Power

If external gate drivers are used to control the cascode devices, then sufficient drive current is provided, but hardware complexity increases and CMTI performance is compromised

Engineering Contradiction:
Improvegate drive currentVSAvoidhardware complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent merges the gate driver functionality directly into the module package, combining the power switching and gate drive functions in a single integrated unit. This eliminates external gate driver components and their associated power supply requirements, reducing hardware complexity while maintaining sufficient drive current capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The integrated gate driver performs multiple functions: providing sufficient drive current for fast switching, generating the gate drive voltages internally without external power supplies, and maintaining galvanic isolation for CMTI performance. This multi-functional integration simplifies the overall system architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Reliability

If external gate drivers with isolated converters are used, then galvanic isolation is provided, but common mode noise is generated and hardware implementation is complicated

Engineering Contradiction:
Improvegalvanic isolationVSAvoidcommon mode noise
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The integrated gate driver is self-powered, generating its own gate drive voltages from the module's internal circuits without requiring external isolated converters. This self-service approach eliminates the sources of common mode noise associated with external isolation circuits while maintaining galvanic isolation through the inherent package design.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances power efficiency, simplifies hardware implementation, improves CMTI performance, and reduces the form factor and cost by utilizing the GaN device's benefits while minimizing losses and parasitic impedance, enabling high-speed switching and power density.

Implementation Method 1

a large capacitor, Cx, is often integrated into the MOSFET die to mitigate the middle point voltage overshoot during the turn-off period

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

The large band gap, high breakdown voltage, and fast switching properties of Gallium Nitride (GaN) make it an ideal candidate for use in high-power semiconductor devices

Methodology Applied
Scientific EffectHall effect: Hall Effect

Data Source

PatentEP4380054A1Cascode switching module
Publication Date: 2024.06.05 NEXPERIA BV
  • EP4380054A1 patent drawingFigure 1
  • EP4380054A1 patent drawingFigure 2
  • EP4380054A1 patent drawingFigure 3~4

AI summary

A cascode transistor circuit comprising a depletion mode semiconductor device, an enhancement mode transistor having a drain terminal connected to a source terminal of the depletion mode semiconductor device, and a gate driver coupled to a first node between the source of the depletion mode semiconductor device and the drain of the enhancement mode transistor. The gate driver is powered by the depletion mode semiconductor device.