Semiconductor Device Control Layer Warping Mitigation
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Solution Overview
Problem
The existing semiconductor devices face challenges in reducing resistance while minimizing the risk of warping and cracking due to the increased thickness of the metal layer in the common drain electrode, which can lead to structural issues during manufacturing and mounting on a wiring substrate.
Innovation Solution
Incorporating a control layer with a smaller linear expansion coefficient than the drain electrode, positioned under the drain electrode, to mitigate bending stress and prevent warping and cracking by sandwiching the drain electrode between the semiconductor layer and the control layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the film thickness of the metal layer of the common drain electrode is increased to reduce resistance, then the resistance in on-operation is reduced, but the semiconductor element region may warp during manufacturing or mounting, and cracks may occur
Solution Approach 1:
The patent introduces a control layer with specifically controlled linear expansion coefficient that is smaller than that of the drain electrode metal layer. This parameter change in the expansion coefficient creates a compensating effect that suppresses warping while maintaining the thick metal layer for low resistance
Solution Approach 2:
The patent creates a composite structure consisting of the semiconductor element region, the thick drain electrode metal layer, and the control layer with different thermal expansion properties. This composite structure allows the control layer to counteract the warping tendency of the metal layer, enabling both low resistance and structural integrity
2Reliability
If the thickness of the semiconductor element region is reduced to reduce resistance, then the resistance in on-operation is reduced, but the semiconductor element region may warp in manufacturing processes or when mounting, and cracks may occur
Solution Approach 1:
The control layer acts as an intermediary between the semiconductor element region and the drain electrode metal layer. It mediates the thermal expansion differences and mechanical stresses, protecting the thin semiconductor element region from warping and cracking while allowing the thick metal layer to provide low resistance
3Reliability
If a thick metal layer is used in the common drain electrode, then low resistance is achieved, but bending stress increases causing warping and potential cracking
Solution Approach 1:
The patent utilizes differential thermal expansion between the control layer and the drain electrode metal layer. The control layer has a smaller linear expansion coefficient, creating a compensating stress that counteracts the bending stress generated by the thick metal layer, thereby preventing warping and cracking
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The control layer effectively suppresses bending stress-induced warping and cracking in the semiconductor layer, maintaining low resistance during operation while preventing defects in the semiconductor device's structure.
Implementation Method 1
the control layer has a smaller linear expansion coefficient than the drain electrode
Data Source
AI summary
A semiconductor device includes a first transistor, a second transistor, a third electrode, and a control layer. The first transistor includes a first region of a semiconductor layer, a first electrode, and a first gate electrode. The first electrode is electrically connected with the first region. The first gate electrode is located in the first region. The second transistor includes a second region of the semiconductor layer, a second gate electrode, and a second electrode. The second region is next to the first region. The second gate electrode is located in the second region. The second electrode is electrically connected with the second region. The third electrode is electrically connected with the first and second transistors. The control layer has a smaller linear expansion coefficient than the third electrode.