3D Nanosheet Transistor Architecture for Leakage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuits to reduce power consumption while increasing operation rates, as individual transistor feature sizes approach physical atomic limitations, leading to issues like leakage currents and short-channel effects in conventional 2D circuit fabrication.
Innovation Solution
A nanosheet-based design is employed using 2D material layers for transistor channels and source/drain contacts, supported by a seed layer, with a gate structure that can surround the channel, enabling a gate-all-around configuration to facilitate continued scaling and reduce leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 2D circuit fabrication techniques are used to scale down transistors, then transistor density increases, but leakage currents and short-channel effects worsen due to physical atomic limitations
Solution Approach 1:
The patent transitions from conventional 2D planar transistor structures to 3D vertical nanosheet-based transistor architectures. Multiple nanosheets are stacked vertically to form channels, enabling continued scaling and improved density while maintaining better electrical control and reduced leakage currents through the vertical configuration and gate-all-around structure
Solution Approach 2:
The gate structure completely surrounds each nanosheet channel in a nested configuration, with the gate wrapping around the channel from all sides. This gate-all-around structure provides superior electrostatic control over the channel, effectively suppressing short-channel effects and leakage currents while maintaining compact device dimensions
2Power
If transistor feature sizes are reduced to approach physical atomic limitations, then power consumption decreases and operation rate increases, but manufacturing precision becomes extremely difficult to maintain
Solution Approach 1:
The patent changes the dimensional parameters of the transistor structure by transitioning to vertically stacked nanosheets with thicknesses on the order of a few atoms. This vertical scaling approach allows continued miniaturization and power reduction while the self-aligned fabrication processes maintain manufacturing precision despite the reduced feature sizes
Solution Approach 2:
The channel region is segmented into multiple discrete nanosheets stacked vertically, each with precisely controlled thickness. This segmentation into thin 2D material layers enables better control over electrical properties and manufacturing precision, as each nanosheet can be independently formed and controlled during fabrication
3Reliability
If gate-all-around structures are implemented to reduce leakage currents, then reliability improves, but device complexity increases
Solution Approach 1:
The gate-all-around structure serves multiple functions simultaneously: it provides electrostatic control of the channel, acts as a barrier against leakage currents, and enables compact device integration. The same surrounding gate configuration can be applied to multiple nanosheets in a stack, reducing overall device complexity through standardized fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows existing IC fabrication facilities to scale down transistors effectively, reducing leakage currents and improving transistor performance while maintaining compatibility with existing manufacturing techniques.
Implementation Method 1
a seed layer formed on silicon nanosheet in order to selectively form or deposit 2D material layer on the seed layers
Data Source
AI summary
One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a source contact, a drain contact, a 2D material forming a channel between the source and drain contacts and surrounding a carrier nanosheet forming a first p-n junction with the source contact and a second p-n junction with the drain contact, and a gate structure comprising a gate dielectric and a gate contact contacting at least a portion of the channel between the first p-n junction and the second p-n junction. The source and drain contacts can comprise a doped semiconductor material and a channel having a first curved profile extending along the source contact and a second curved profile extending along the drain contact.