3D Neural Network Array With Stacked Conductive Layers

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Solution Overview

Problem

Conventional neural networks face limitations in density and speed, which hinder their performance in real-time tasks, especially for high-density applications.

Innovation Solution

A novel 3D neural network array structure is introduced, featuring stacked input layers, hidden layers with in-line threshold elements, and synapse elements with programmable resistive elements, enabling higher density and speed through variable resistance values and threshold functions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional neural networks are implemented using software on CPU, then flexibility and programmability are maintained, but processing speed becomes a bottleneck for real-time tasks

Engineering Contradiction:
Improveprocessing speedVSAvoidCPU computational complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical/software-based CPU computation system with a hardware-based neural network array that performs computations through physical electrical signal propagation and resistive element interactions, enabling parallel processing of all neural operations simultaneously rather than sequential execution

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent transitions from two-dimensional planar circuit layouts to three-dimensional vertical stacking of conductive layers, allowing multiple input layers, hidden layers, and output layers to be integrated in the vertical dimension, dramatically increasing network density and processing capacity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If hardware implementation is used for neural networks, then processing speed improves for real-time applications, but circuit size limits the density and functionality of the network

Engineering Contradiction:
Improvereal-time processing capabilityVSAvoidcircuit area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent employs three-dimensional vertical stacking of conductive layers to increase network density without expanding the planar footprint, allowing multiple neural network layers to be integrated within the same chip area through vertical arrangement rather than horizontal expansion

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested conductive structures where input conductors, hidden conductors, and output conductors are arranged in concentric or interleaved patterns, with multiple conductive layers nested within each other vertically, maximizing the use of available space and increasing network density

Inventive Principle:
Principle #7Nested doll (Nesting)

3Ease of manufacture

If typical circuit sizes are used, then manufacturing simplicity is maintained, but the density and size of the neural network are limited

Engineering Contradiction:
Improvecircuit fabrication simplicityVSAvoidneural network density
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent achieves high density by stacking conductive layers in the vertical dimension while maintaining compatibility with standard planar semiconductor manufacturing processes, allowing complex 3D structures to be fabricated using conventional layer-by-layer deposition and patterning techniques

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the neural network into discrete modular layers (input layers, hidden layers, output layers) that can be independently fabricated and then stacked, allowing each layer to be manufactured separately using standard processes and assembled into the final 3D structure

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The 3D neural network array achieves significantly higher density and speed compared to conventional networks, enhancing its capability for real-time tasks and complex learning processes.

Implementation Method 1

Each synapse element includes a programmable resistive element

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS11205116B2Three-dimensional neural network array
Publication Date: 2021.12.21 HSU FU CHANG
  • US11205116B2 patent drawing
  • US11205116B2 patent drawing
  • US11205116B2 patent drawing

AI summary

Three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network includes a plurality of input conductors forming a plurality of stacked input layers having a first orientation, and at least one output conductor forming an output layer having the first orientation. The three-dimensional (3D) neural network also includes a plurality of hidden conductors having a second orientation. Each hidden conductor includes an in-line threshold element. The three-dimensional (3D) neural network also includes synapse elements coupled between the hidden conductors and the input conductors and between the hidden conductors and the output conductor. Each synapse element includes a programmable resistive element.