Neural Architectures TRIZ Cases
- Neural Network Continual Learning via Architectural Search
A training module generates task-specific neural networks through architectural search on shared layers to maintain performance across sequential tasks.
- Neural Network Compression via Pruning Quantization and Distillation
Pruning and quantizing an initial neural network creates a teacher model that guides student training, addressing performance drops in small models.
- Dynamic Neural Network Batching Controller for Latency Reduction
A dynamic batching controller adjusts neural network layer sizes based on operation ratios.
- Neuromorphic Synapse Gating Pulse Resistance Control
A neuromorphic synapse uses a gating pulse to adjust memristor resistance change ratios for precise synaptic weight training.
- Intermediate Representation Memory Management via Execution Tracking
A system manages intermediate representations by extracting data and operation information to generate a structured representation for processing.
- DNN Image Sensor Trigger Control for Power Reduction
Dynamic trigger signals switch the DNN process between operation and stop states, reducing power consumption during idle periods.
- Matrix Multiplication Optimization Using Vector Registers
Loads non-zero elements into vector registers to reduce computing power consumption during neural network operations.
- Distributed Neural Network Training on Edge Devices
Segmenting neural networks across edge devices eliminates centralized processing bottlenecks while preserving data privacy and reducing communication overhead.
- Neural Network Multiplexing Layer for High-Throughput Processing
Multiplexing layers combine multiple inputs into a single compact representation, reducing energy consumption while maintaining model performance.
- Neural Network Node Assemblies for Information Processing
Node assemblies with high within-assembly connectivity improve information processing performance while managing network organization complexity.
- 3D Neural Network Array With Stacked Conductive Layers
Stacked input, hidden, and output conductors with programmable resistive elements resolve the trade-off between real-time processing speed and circuit area.
- Hierarchical Predictive Model Building for Large Datasets
A hierarchical method preprocesses datasets and clusters them to build predictive models in a layered approach.
- Dynamic Matrix Convolution Channel Fusion
A dynamic convolution neural network compresses input data into a low-dimensional intermediate space to fuse channels efficiently.
- DUnet Architecture for Seismic Data Denoising
A DUnet engine processes seismic data using contractive and expansive paths to produce denoised images.
- Weighted F-Measure for Multiclass Classifier Evaluation
A weighted f-measure metric computes class-specific precision and recall weights to evaluate multiclass classifiers.
- Neural Network Multiplexing Circuit for Feature Map Data Extraction
A multiplexing circuit extracts feature data from buffer cells to accelerate neural network operations.
- Neural Network Pruning via Sensitivity Regularization
Joint parameter promotion achieves structured sparsity, reducing non-zero parameters while preserving network structure and memory access efficiency.
- JPAT Neural Network Architecture Reduces Training Time
Joint Proximity Association Template replaces CNN proximal layers with associative memory matrices to accelerate neural network processing.
- Multi-iteration Neural Network Compression via Sensitivity-Based Pruning
Sensitivity-based pruning reduces storage requirements and computational load in speech recognition models while maintaining high measurement precision.
- Block-Based CNN Inference Reducing DRAM Bandwidth via Feature Reuse
A block-based inference method divides input images into blocks to process convolution operations independently.
- Storage Compute Device Neural Network Context Switching
Dynamic context switching in a storage compute device reduces data transfer time by processing large matrices directly within non-volatile memory arrays.