Neural Network Multiplexing Circuit for Feature Map Data Extraction

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Solution Overview

Problem

Neural network devices face challenges in efficiently processing complex input data, requiring a method to extract necessary data using fewer resources and reducing power consumption for real-time analysis.

Innovation Solution

An integrated circuit with a buffer and multiplexing circuit that stores feature map data in units of cells and extracts feature data corresponding to identical coordinate values, using a smaller number of multiplexers to generate extracted data for neural network operations, which can be rearranged for efficient computation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a conventional method is used to extract feature data from feature map data for neural network operations, then the data extraction can be performed, but it requires a large number of resources and high power consumption

Engineering Contradiction:
Improvepower consumptionVSAvoiddata extraction speed
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The feature map data is divided into multiple cells, with each cell containing feature data for a specific coordinate position. This segmentation allows the multiplexing circuit to efficiently select and extract feature data from different cells simultaneously, reducing the overall power consumption while maintaining extraction speed

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The multiplexing circuit is designed to handle multiple coordinate values and feature types through a unified structure. By using a small number of multiplexers that can be configured to select from different cells based on coordinate values, the circuit achieves multi-functionality without requiring dedicated extraction paths for each coordinate, thus reducing resource usage and power consumption

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Speed

If more resources are allocated for data extraction, then the data extraction speed can be improved, but the chip area occupation increases

Engineering Contradiction:
Improvedata extraction speedVSAvoidchip area
Core Design Contradiction:
SpeedVSArea of stationary object

Solution Approach 1:

Multiple feature data selections for different coordinate values are merged into a single multiplexing circuit structure. Instead of having separate extraction circuits for each coordinate, the patent combines them into one circuit that can be configured to select from different cells, thereby reducing chip area while maintaining extraction speed

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent organizes feature map data in a three-dimensional structure (cells × coordinates × features), allowing the multiplexing circuit to operate along the cell dimension. This dimensional organization enables efficient data extraction without requiring proportional increases in circuit complexity or chip area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If a smaller number of multiplexers is used, then the chip area and power consumption are reduced, but the complexity of data extraction increases

Engineering Contradiction:
Improvenumber of multiplexersVSAvoidextraction efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The multiplexing circuit uses dynamic control signals to select which cell's feature data to extract based on the coordinate value. This dynamic configuration allows a small number of multiplexers to handle multiple coordinate values efficiently, maintaining extraction efficiency while reducing the number of hardware components

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces cell identifiers as an intermediary mechanism that mediates between the coordinate information and the multiplexer selection. This intermediary allows the multiplexing circuit to efficiently route feature data from the correct cell without requiring complex direct addressing logic, thus maintaining extraction efficiency with fewer multiplexers

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12198053B2Integrated circuit that extracts data, neural network processor including the integrated circuit, and neural network device
Publication Date: 2025.01.14 SAMSUNG ELECTRONICS CO LTD
  • US12198053B2 patent drawing
  • US12198053B2 patent drawing
  • US12198053B2 patent drawing

AI summary

An integrated circuit included in a device for performing a neural network operation includes a buffer configured to store feature map data in units of cells each including at least one feature, wherein the feature map data is for use in the neural network operation; and a multiplexing circuit configured to receive the feature map data from the buffer, and output extracted data by extracting feature data of one of features that are included within a plurality of cells in the received feature map data, the features each corresponding to an identical coordinate value.