3D NOR Flash Memory With Isolated Source Lines
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Solution Overview
Problem
Conventional flash memory technologies face limitations in storage capacity and reliability, particularly in three-dimensional structures, where interference during reading operations and damage to the tunneling dielectric layer are concerns.
Innovation Solution
The implementation of a three-dimensional memory structure with isolation structures between source lines to reduce interference and the use of a high dielectric constant material for charge storage, enabling four bits to be stored in a single memory cell, along with a band-to-band hot hole injection mode for erasure, which minimizes damage to the tunneling dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation structures are added between source lines to reduce interference, then reading reliability is improved, but device complexity increases
Solution Approach 1:
The patent divides the source line structure into isolated segments by introducing isolation structures between adjacent source lines. This segmentation prevents electrical interference and coupling between neighboring source lines, thereby improving reading reliability while maintaining a manageable device architecture through systematic division rather than complex interconnections
2Quantity of substance
If high dielectric constant material is used for charge storage to increase storage capacity, then storage capability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs high dielectric constant materials (such as hafnium oxide, aluminum oxide, or tantalum oxide) as the charge storage layer in the memory structure. These composite materials provide superior charge retention capabilities and enable higher storage density by allowing smaller feature sizes and thinner tunneling dielectric layers, thereby increasing the quantity of storable charge while the fabrication process is optimized to meet the precision requirements
3Reliability
If band to band hot hole injection mode is used for erasure, then tunneling dielectric layer damage is reduced, but erasure time increases
Solution Approach 1:
The patent utilizes band to band hot hole injection for memory cell erasure, which changes the physical mechanism from direct tunneling to impact ionization. By adjusting voltage parameters and applying appropriate electric field strengths, hot holes are generated and injected into the charge storage layer, effectively erasing data while minimizing damage to the tunneling dielectric layer. The process optimizes the balance between erasure effectiveness and dielectric layer preservation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances storage capacity and reliability by reducing interference during read operations and minimizing damage to the tunneling dielectric layer, thereby improving the overall performance of three-dimensional memory devices.
Implementation Method 1
The isolation structures are respectively located between the source lines so as to electrically isolate the source lines from each other
Implementation Method 2
the invention utilizes a high dielectric constant material as a charge storage layer which can store a data of four bits in a single memory cell
Implementation Method 3
the invention erases the memory cell via a band to band hot hole injection mode which can reduce damage caused to the tunneling dielectric layer
Data Source
AI summary
A three dimensional memory includes a substrate, a plurality of source lines, a plurality of isolation structures, a plurality of drain lines, a plurality of bit lines, a plurality of charge storage structures, and a plurality of conductive layers. The source lines are located on the substrate. The isolation structures are respectively located between the source lines, so as to electrically isolate the source lines from each other. The drain lines are located on the source lines. Extending directions of the source lines and the drain lines are different. The bit lines extend from the source lines to the drain lines. The charge storage structures respectively surround the bit lines. The conductive layers respectively cover surfaces of the charge storage structures arranged along each of the source lines.