Transistor TRIZ Cases

A semiconductor fabrication method uses spacer patterns and polymer blocks to define contact holes within the cell area.

Vertical transfer gates in 3D pixels boost charge movement speed while maintaining high pixel density.

Deep ion implantation increases channel capacitance in NAND substrates, reducing gate-induced drain leakage and program disturb.

Replacing linear capacitors with a gated diode enables voltage gain greater than one, boosting sensing signal strength beyond conventional DRAM limits.

A thin film resistor structure uses a dummy layer with recessed regions filled with polishing resistance material to minimize dishing and erosion effects.

Segmented flash lamp and microwave annealing fixes crystal defects and activates impurity ions without excessive diffusion, preventing junction leakage.

Switchable balance resistors suppress parasitic oscillation during turn-off while maintaining low turn-on loss through dynamic resistance adjustment.

A stacked thin-film transistor extends the effective channel length within a confined pixel area to support dual conduction paths.

Parallel capacitor and resistor across the gate and emitter provide a strong pull-down to limit peak collector-to-emitter voltage.

A bi-directional protection circuit employs a single comparator with diodes to detect overcurrent faults.

Isolation structures between source lines reduce read interference while high dielectric materials enable four bits per cell.

An integrated decoder merges selection and reset lines to eliminate separate decoders, reducing space while enabling global reset and blooming control.

Shared gate mask integration merges planar and vertical FETs, resolving I/O performance limits while maintaining high device density.

A vertical fin field-effect transistor uses segmented source and drain regions to define the channel geometry.

An oxide semiconductor thin film transistor employs an independent bias electrode to suppress threshold value shifts and reduce power consumption.

Nitrogen masking material prevents oxygen etchant damage to ruthenium, ensuring accurate conductive line patterning.

A multi-electrode high-voltage transistor isolates a field electrode to minimize parasitic capacitances and reduce switching power loss.

Selective etching creates a core region for dielectric deposition and metal contacts that adjust threshold voltage without increasing fabrication complexity.

An active fin with a recess allows the gate electrode to extend onto side surfaces, increasing channel width and length without expanding device area.

A single poly multi time programmable cell uses a sensing transistor and control gate to enable efficient program and erase operations.

A stacked polysilicon resistor structure with an inter-resistor insulating layer achieves precise resistance control through vertical series connection.

Segmented read transistors increase parasitic capacitance to amplify weak capacitor signals, reducing read errors caused by insufficient voltage difference.

Charge-trapping layers near source regions reduce contact resistance and improve sub-threshold slope in 2D material FETs.

A semiconductor capacitor formation method uses layered molding structures to expose electrode surfaces for precise dielectric deposition.

A recessed fin transistor uses epitaxial source-drain regions surrounded by conductive metal to form an all-around contact structure.

Non-planar MOSFETs with extended drains reduce off-state leakage currents while increasing snapback current conduction for integrated circuits.

A semiconductor structure embeds a silicon-controlled rectifier within FinFET fins to reduce footprint.

A centralized overvoltage protection arrangement uses a voltage limiting unit to bias semiconductor switches into conduction.

A thin-film device transfer method bonds a layered structure to a substrate using adhesive delamination.

Parasitic bipolar transistors lower the trigger voltage of an ESD protection device, preventing damage to protected circuitry before activation.

Segmented isolation regions block current leakage while reducing parasitic capacitance to maintain high integration density.

Hydrogen annealing creates a gap for epitaxial growth, reducing junction gradients and series resistance while minimizing fin damage.

Segmented doped and undoped polysilicon layers prevent seam voids during etching, preserving contact surface area and reducing resistance defects.

A semiconductor device uses segmented gate electrodes and stacked nanosheets to optimize structure.

Common electrode lines and drain extensions form a light blocking structure that reduces edge light leakage, improving liquid crystal deflection.

Ammonium hexafluorosilicate generation enhances etching selectivity, reducing nitride loss and current leakage while stabilizing air gap formation.

Selective etching exposes semiconductor bars for coating with a strained material, maintaining stress stability and preventing dopant diffusion.

A semiconductor stack uses c-axis aligned oxide layers to enhance electrical conductivity and device reliability.

Dual stop layers segment the etching process to prevent direct penetration of contact plugs through metal gates, thereby improving device reliability.

An N well guard ring increases impedance to suppress noise conduction through the seal ring, preventing device malfunction.

Curved sidewalls in sacrificial layer recesses boost capacitance while preventing structural collapse during DRAM processing.

A silicon carbide trench MOSFET forms a gate insulating film along side surfaces to reduce channel resistance.

Segmented capacitor units across multiple rows stabilize power supply voltage while minimizing unused area in logic circuit blocks.

Localized parameter changes increase fin width and pitch to resolve dopant implantation damage while maintaining device density.

Vertical gate contacts reduce parasitic capacitance while recessed spacers create air gaps to maintain manufacturing yields.

Multi-stacked CMOS transistors with substrate body switching and external capacitors enable high-power RF signal routing.

Bipolar transistor breakdown voltage replaces resistor dividers for input detection, reducing current consumption and circuit complexity.

A CMOS metal gate structure uses a sacrificial layer to diffuse dopants into barrier layers for precise threshold voltage control.

A segmented oxide semiconductor transistor structure adjusts the distance between low-resistance regions to improve withstand voltage characteristics.

Skewed fin orientation decouples channel length from cell area, reducing short channel effects in 5 nm SRAM.