Thin Film Resistor Dummy Layer CMP Dishing Mitigation
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Solution Overview
Problem
Conventional thin film resistors in semiconductor integrated circuits face issues such as CMP dishing and erosion due to the long extension of polysilicon line structures, leading to over-polishing and over-etching, which are not satisfactorily addressed by existing methods.
Innovation Solution
A thin film resistor is formed with a metal thin film disposed above a semiconductor substrate and a dummy layer, where recessed regions in the dummy layer are filled with polishing resistance material to minimize dishing and erosion effects during the CMP process, allowing for concurrent formation with MOSFETs and compatibility with CMOS fabrication technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a CMP process is performed on a substantially long polysilicon line structure to form the metal gate and contacts of the thin film resistor, then the thin film resistor can be formed concurrently with the metal gate, but CMP dishing and erosion effects occur leading to over-polishing and over-etching
Solution Approach 1:
The patent introduces a dummy layer with non-uniform thickness profile (thinner at ends, thicker in middle) that creates localized variations in polishing resistance. This local quality difference allows the CMP process to be controlled differently at different positions, preventing dishing and erosion at the polysilicon line structure while maintaining concurrent formation capability.
Solution Approach 2:
The dummy layer acts as an intermediary element between the CMP polishing pad and the polysilicon line structure. By positioning the dummy layer laterally adjacent to the polysilicon line structure and having it extend beyond the metal gate, it serves as a buffer that absorbs excess polishing action, protecting the polysilicon line structure from over-polishing and the contacts from over-etching.
2Ease of manufacture
If the polysilicon line structure extends substantially long to overlay the metal thin film, then the metal gate and contacts can be formed, but dishing and erosion effects occur
Solution Approach 1:
The patent converts the harmful dishing and erosion effects into a beneficial control mechanism. By intentionally designing the dummy layer with specific thickness variations, the polishing-induced material removal becomes a controlled process that shapes the dummy layer in a desired pattern while protecting adjacent structures, effectively turning the harmful CMP effects into a useful self-aligning and self-limiting mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of polishing resistance material in recessed regions of the dummy layer effectively reduces dishing and erosion, enabling the formation of reliable thin film resistors with improved process compatibility and reduced defects.
Implementation Method 1
a chemical-mechanical polishing (CMP) process is performed on a substantially long polysilicon line structure that overlays the metal thin film
Data Source
AI summary
A semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material.