Planar Insulating Layer for Leakage Control in Semiconductor Devices
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Solution Overview
Problem
Semiconductor devices face challenges in reducing size while minimizing current leakage and parasitic capacitance, which are limitations in three-dimensional structures.
Innovation Solution
A semiconductor device design incorporating a planar insulating layer with different permittivity layers and nanosheets to extend the leakage path and reduce parasitic capacitance, including a substrate with a protrusion and nanosheets, where the planar insulating layer is formed between the substrate and nanosheets, and the gate electrode surrounds the nanosheets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a three-dimensional structure is used to reduce device size, then device capacity increases, but current leakage and parasitic capacitance increase
Solution Approach 1:
The substrate surface is segmented into multiple isolation regions separated by grooves, with insulating layers filling these grooves. This segmentation creates discrete isolation zones that effectively block current leakage paths between adjacent device regions while maintaining compact device spacing.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between the substrate and device structures, and between adjacent device regions. These intermediary insulating layers act as electrical isolators that prevent direct current leakage paths while allowing the device structures to maintain their three-dimensional configuration.
2Volume of moving object
If a three-dimensional structure is used to reduce device size, then device capacity increases, but parasitic capacitance increases
Solution Approach 1:
The substrate surface is segmented into multiple isolation regions separated by grooves, with insulating layers filling these grooves. This segmentation creates discrete isolation zones that effectively block current leakage paths between adjacent device regions while maintaining compact device spacing.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between the substrate and device structures, and between adjacent device regions. These intermediary insulating layers act as electrical isolators that prevent direct current leakage paths while allowing the device structures to maintain their three-dimensional configuration.
3Productivity
If device size is reduced, then integration density increases, but leakage path control becomes more difficult
Solution Approach 1:
The substrate surface is segmented into multiple isolation regions separated by grooves, with insulating layers filling these grooves. This segmentation creates discrete isolation zones that effectively block current leakage paths between adjacent device regions while maintaining compact device spacing.
Solution Approach 2:
The isolation structure extends into the vertical dimension with grooves etched into the substrate and insulating layers deposited within these grooves. This vertical dimensionality provides additional leakage blocking capability without increasing horizontal device footprint, thereby maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively minimizes current leakage and reduces parasitic capacitance, enhancing current characteristics and efficiency of the semiconductor device.
Implementation Method 1
The planar insulating layer includes first and second insulating layers having different permittivities
Data Source
AI summary
A semiconductor device includes a substrate. A planar insulating layer is disposed on an upper surface of the substrate. A channel region is disposed above the planar insulating layer. A gate electrode is disposed on the channel region. The semiconductor device includes a source region and a drain region. Each of the source region and the drain region is disposed on the substrate and is connected to the channel region. The planar insulating layer has a length equal to or greater than a length of the channel region, and the planar insulating layer includes first and second insulating layers having different permittivities.