Vertical FinFET Gate Length Control via Segmented Source-Drain
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The fabrication of vertically-oriented FinFETs faces challenges in controlling gate length, forming extension regions, and maintaining symmetry, which complicates integration with existing process flows.
Innovation Solution
A vertically-oriented field-effect transistor device is fabricated using a semiconductor substrate stack with lightly doped extension regions and a fin channel region, where a gate structure is formed along the sidewalls of the fin channel, enabling a conductive channel between source/drain regions perpendicular to the substrate, and a method involving selective etching and planarization processes to define the fin channel structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertically-oriented FinFET structure is adopted, then short channel effect control and current drive are improved, but manufacturing complexity and integration difficulty increase
Solution Approach 1:
The extension regions are formed prior to the gate structure formation, establishing the vertical channel architecture in advance. This preliminary formation of source/drain regions with extension portions simplifies subsequent processing steps and maintains symmetry in the vertical FinFET structure.
Solution Approach 2:
The invention transitions from planar MOSFET geometry to vertically-oriented FinFET structure with channels perpendicular to the wafer surface. This dimensional change enables better short channel control while the specific formation sequence (extension regions before gate) manages the manufacturing complexity introduced by this vertical architecture.
2Manufacturing precision
If gate length control is tightened for smaller technology nodes, then device scaling is improved, but formation difficulty and symmetry maintenance become more challenging
Solution Approach 1:
The extension regions are formed with controlled dimensions before gate patterning, establishing precise vertical boundaries that define the future gate length. This preliminary definition of channel boundaries simplifies the subsequent gate formation process and ensures symmetry in the vertical FinFET structure.
Solution Approach 2:
The source/drain regions are segmented into distinct portions including extension regions with different doping concentrations and geometries. This segmentation allows independent optimization of each region's dimensions and properties, enabling precise gate length control while simplifying the overall formation process through modular construction.
Data Source
AI summary
A FinFET-type device is formed having a fin structure with vertically-oriented source/drain regions (with lightly doped extensions) and a channel region extending substantially perpendicular to the surface of the semiconductor substrate. A semiconductor stack is provided (or formed) having a first heavily doped layer and two lightly doped layer, with a channel region formed between the two lightly doped layers. The stack is etched to form fin structures (for the devices) and a gate stack is formed along the sidewalls of the channel region. A second heavily doped layer is selectively formed on the upper lightly doped layer. A portion of the first heavily doped layer and a portion of the lower lightly doped layer form a lower S/D region with a lightly doped extension region. Similarly, a portion of the second heavily doped layer and a portion of the upper lightly doped layer form an upper S/D region with a lightly doped extension region.