Stacked Polysilicon Resistor for Stable Resistance Control
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Solution Overview
Problem
Conventional semiconductor devices face challenges in forming small-sized contact plugs through thick insulating layers, which complicates the integration of resistors in high-density semiconductor devices, and existing resistor structures do not provide stable and controlled resistance values.
Innovation Solution
A semiconductor device design featuring a lower resistor with a high and stable resistance value, combined with an upper resistor that exposes both ends and is connected in series, along with an inter-resistor insulating layer, to achieve precise resistance control and reduce resistance variance, using polysilicon and metal nitride layers for the resistors and silicon oxide and high-k dielectric layers for the insulating components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a thick insulating layer is interposed between the resistor and metal interconnection, then the resistor can be formed at the same time as the gate electrode, but it complicates the formation of small-sized contact plugs
Solution Approach 1:
The patent transitions from a planar resistor structure to a three-dimensional stacked structure by placing an upper resistor layer above the lower resistor layer. This vertical arrangement allows contact plugs to access resistor terminals through the insulating layer without requiring the plugs to traverse the entire thickness of multiple insulating layers, thereby simplifying contact plug formation while maintaining efficient resistor integration
Solution Approach 2:
The upper resistor layer is positioned to cover and overlap with the lower resistor layer, creating a nested configuration where the upper layer effectively 'contains' the lower layer's terminal regions. This nesting allows shared contact structures to access both resistor layers through the same contact plug openings, reducing the number and size of contact plugs required
2Adaptability or versatility
If a polysilicon layer is used for both gate electrode and discrete resistor, then material consistency is achieved, but the polycide layer used as gate electrode is no longer appropriate for resistor formation
Solution Approach 1:
The patent divides the resistor structure into two separate layers: a lower resistor layer formed from the gate electrode polysilicon layer, and an upper resistor layer formed from a dedicated resistor material layer. This segmentation allows each layer to be optimized for its specific function - the lower layer maintains compatibility with gate electrode processes while the upper layer provides stable resistance characteristics
Solution Approach 2:
The patent employs a composite resistor structure combining two different materials: polysilicon for the lower resistor layer and a separate resistor material (such as doped polysilicon or metal silicide) for the upper resistor layer. This composite approach leverages the advantages of both materials - the process compatibility of polysilicon and the stability of dedicated resistor materials
3Ease of manufacture
If resistors are formed with conventional methods, then simple fabrication is achieved, but resistance distribution and variance are not controlled
Solution Approach 1:
The patent introduces a vertical stacking dimension to resistor formation, creating multiple resistor layers at different heights. This three-dimensional configuration provides additional degrees of freedom for controlling resistance characteristics through layer thickness, material composition, and geometric arrangement, enabling precise resistance control while maintaining fabrication simplicity
Solution Approach 2:
The patent controls resistance values by adjusting multiple parameters including the thickness of each resistor layer, the doping concentration of polysilicon regions, the material composition of the upper resistor layer, and the overlapping geometry between layers. These parameter variations enable precise control of resistance distribution and variance without complicating the fabrication process
Data Source
AI summary
In a semiconductor device having a resistor and a method of fabricating the same, the device includes a semiconductor substrate having a cell region and a peripheral region. A lower interlayer insulating layer is disposed on the semiconductor substrate. A buffer pad is disposed on the lower interlayer insulating layer in the cell region. A capacitor is provided to have a storage node electrode disposed on the buffer pad, a plate electrode covering the storage node electrode, and a capacitor dielectric is interposed between the storage node electrode and the plate electrode. A lower resistor is disposed on the lower interlayer insulating layer in the peripheral region. An upper resistor is disposed on the lower resistor to expose both ends of the lower resistor. An inter-resistor insulating layer is interposed at least between the lower resistor and the upper resistor. An upper interlayer insulating layer is disposed on the lower interlayer insulating layer to cover the capacitor, the lower resistor, and the upper resistor. A resistor interconnection line is disposed on the upper interlayer insulating layer, to contact a resistor contact plug penetrating the upper interlayer insulating layer and is electrically connected to a first end of the lower resistor and a first end of the upper resistor.