CMOS Metal Gate Threshold Voltage Adjustment via Dopant Diffusion
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Solution Overview
Problem
As semiconductor devices shrink in size, the conventional metal gate structures face challenges in accurately adjusting threshold voltage and maintaining electrical characteristics due to issues like gate leakage, complex gate structures, and difficulties in filling metal layers, especially in FinFET devices with 3D channels.
Innovation Solution
A CMOS device with a novel metal gate structure and manufacturing method that includes a gate stack with specific barrier layers and work function adjusting layers, utilizing a sacrificial layer to diffuse dopants and improve the accuracy of threshold voltage adjustment, and a method that forms gate trenches and deposits high-k gate insulating layers, followed by barrier and work function layers to enhance filling and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the conventional metal gate structure is used with shrinking device size, then the gate leakage is suppressed by reducing EOT, but the gate leakage becomes serious due to ultrathin conventional oxide layer
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate insulating layer from conventional oxide (k≈3.9) to high-k material (k≥7), allowing thicker physical thickness while maintaining equivalent oxide thickness, thus suppressing gate leakage without requiring ultrathin layers
Solution Approach 2:
The patent uses a composite gate stack structure combining high-k gate insulating layer with metal gate layer, creating a composite material system that achieves both low leakage and controllable threshold voltage
2Manufacturing precision
If multiple stack layers are deposited and selectively removed to adjust threshold voltage, then the threshold voltage adjustment is achieved, but the gate structure becomes over-complex
Solution Approach 1:
The patent extracts and removes the sacrificial layer after it has served its purpose of enabling precise threshold voltage adjustment through dopant diffusion, simplifying the final gate structure while maintaining the desired electrical characteristics
Solution Approach 2:
The sacrificial layer acts as an intermediary element that facilitates precise threshold voltage control through controlled dopant diffusion into the barrier layer, then is removed to leave a simplified final structure
3Length of moving object
If the gate length is reduced, then the device size is shrunk, but the space for filling layer with lower resistance is decreased leading to uneven filling and cavity formation
Solution Approach 1:
The patent changes the resistivity parameter of the gate stack by optimizing barrier layer thickness and material composition, reducing the need for thick low-resistance filling layers even in shortened gates
4Manufacturing precision
If the thickness of barrier layer or work function layer is adjusted to control threshold voltage, then the threshold voltage is adjusted, but the adjusting accuracy cannot be effectively improved due to continuous shrinking of device size
Solution Approach 1:
The patent replaces the mechanical approach of adjusting layer thickness with chemical doping of the barrier layer, where threshold voltage is controlled by dopant concentration and diffusion depth rather than physical thickness, enabling finer control as device dimensions shrink
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively improves the accuracy of threshold voltage adjustment and overall device performance by using a sacrificial layer to diffuse impurities into barrier layers, facilitating better metal gate filling and electrical characteristics in both planar and FinFET CMOS devices.
Implementation Method 1
a sacrificial layer is utilized to diffuse impurity to the barrier layer
Implementation Method 2
an annealing temperature of the metal gate
Data Source
AI summary
An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function. The semiconductor device and the method for manufacturing the same according to the present disclosure utilize the sacrificial layer to diffuse impurity to the barrier layer so that the adjusting accuracy of the threshold voltage may be effectively improved, thereby facilitating in improving the whole performance of the device.