Semiconductor Memory Air Gap Etching via (NH4)2SiF6 Vapor
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Solution Overview
Problem
Current semiconductor memory devices face issues with current leakage due to bonding between silicon oxide and silicon interfaces, leading to inefficiencies in air gap formation and nitride loss, which complicates the manufacturing process and requires additional patterning steps.
Innovation Solution
A method involving the formation of a bit line structure sandwiched by air gaps, where a barrier layer overlays spacers, and hydrogen fluoride vapor etching is used to generate (NH4)2SiF6, enhancing the etching rate and controlling the vaporization rate to achieve a desired air gap profile, eliminating the need for additional patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a smaller spacer oxide open area is used, then the HF vapor etching time increases, but the air gap depth becomes insufficient and nitride loss occurs
Solution Approach 1:
The patent changes the physical-chemical parameters of the etching process by introducing (NH4)2SiF6 vaporization. By controlling the vaporization rate of (NH4)2SiF6, the etching rate is enhanced, allowing sufficient air gap depth to be achieved in shorter HF vapor etching time. This parameter change resolves the contradiction between etching time and air gap depth.
Solution Approach 2:
The patent introduces (NH4)2SiF6 as an intermediary substance that mediates the etching process. The (NH4)2SiF6 vaporizes and reacts with the spacer oxide, generating HF in situ, which then etches the oxide to form the air gap. This intermediary mechanism enhances etching efficiency and controls the process to prevent nitride loss while achieving sufficient air gap depth.
2Loss of time
If a larger spacer oxide open area is used, then the HF vapor etching time decreases, but nitride loss increases causing sealed nitride topography
Solution Approach 1:
The (NH4)2SiF6 intermediary controls the etching reaction to be more selective. It vaporizes and reacts preferentially with spacer oxide rather than nitride, enabling shorter etching times without causing nitride loss. This resolves the contradiction between reducing etching time and preventing nitride loss.
Solution Approach 2:
By changing the etching chemistry through (NH4)2SiF6 vaporization, the patent achieves faster etching rates with improved selectivity. The controlled vaporization rate allows precise control over the etching process, reducing overall etching time while maintaining nitride layer integrity and preventing sealed nitride topography.
3Loss of time
If the spacer oxide height is increased, then the open area increases and HF vapor etching time decreases, but air gaps form at high positions causing current leakage
Solution Approach 1:
The (NH4)2SiF6 intermediary enables controlled etching that progresses uniformly through the spacer oxide. By controlling the vaporization rate, the etching front is maintained at the appropriate position, ensuring air gaps form at correct heights rather than high positions. This prevents current leakage between bit lines while maintaining efficient etching time.
Solution Approach 2:
The patent implements process control through monitoring and adjusting the (NH4)2SiF6 vaporization rate. This feedback mechanism ensures the etching process stops at the appropriate depth, preventing air gaps from forming too high and causing current leakage, while still achieving the benefits of reduced etching time.
4Reliability
If greater air gap depth is achieved, then current leakage is reduced, but nitride loss increases causing sealed nitride topography requiring additional patterning
Solution Approach 1:
By changing the etching chemistry through (NH4)2SiF6 vaporization and controlling the vaporization rate, the patent achieves enhanced etching rates with improved selectivity. This allows sufficient air gap depth to be formed for current leakage reduction, while the controlled process prevents excessive nitride loss and sealed nitride topography, eliminating the need for additional patterning steps.
Solution Approach 2:
The (NH4)2SiF6 intermediary provides selective etching that achieves the required air gap depth for reducing current leakage while protecting the nitride layer. The controlled vaporization and in-situ HF generation mechanism ensures precise depth control without causing the sealed nitride topography that would require additional patterning processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces current leakage and nitride loss, stabilizes air gap formation, and eliminates the need for separate patterning of cell and periphery areas, improving the manufacturing efficiency of semiconductor memory devices.
Implementation Method 1
etching the spacer oxide layer from the concavity using a hydrogen fluoride vapor to generate (NH4)2SiF6(s) so as to form an air gap
Implementation Method 2
etching the spacer oxide layer from the concavity using a hydrogen fluoride vapor to generate (NH4)2SiF6(s)
Data Source
AI summary
The present disclosure provides to a method for manufacturing a semiconductor memory device. The method includes receiving a substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area; depositing a landing pad above the barrier layer and on the top surface of the first bit line structure; removing a top corner of the landing pad to form an inclined surface connecting a top surface of the landing pad to a sidewall of the landing pad; etching the nitride layer of the first bit line structure and the spacer nitride layer from the top opening so as to form a concavity;etching the spacer oxide layer from the concavity to form an air gap; and depositing a silicon nitride layer to seal the air gap.