CMOS Antenna Switch Multi-Stacking Body Switching
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Solution Overview
Problem
Current CMOS technology faces challenges in implementing RF switches due to lossy substrates, low electron mobility, and low breakdown voltages, making it unsuitable for multi-band operation and high-power applications.
Innovation Solution
A CMOS RF switch is developed using a multi-stacked transistor with substrate body switching and external components like capacitors to enhance power handling and reduce leakage current, enabling operation across multiple frequency bands (e.g., 900 MHz, 1.9 GHz, and 2.1 GHz) with improved power blocking and low insertion loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CMOS technology is used for RF switches, then integration with other devices and circuits is improved, but power handling capability and breakdown voltage deteriorate
Solution Approach 1:
The RF switch is divided into multiple stacked transistor stages (first stage, second stage, third stage) with different functions. The first stage handles signal routing with low insertion loss, the second stage provides power blocking, and the third stage offers additional isolation. This segmentation allows each stage to be optimized for its specific function, enabling CMOS technology to achieve both good integration and adequate power handling.
Solution Approach 2:
A substrate body switching mechanism is introduced as an intermediary between the transistor stages and the substrate. By selectively connecting or disconnecting the substrate bodies of the transistors, the patent enables dynamic control of power blocking and signal paths without requiring high breakdown voltage transistors, thus allowing CMOS devices to handle higher power levels while maintaining integration benefits.
2Ease of manufacture
If standard CMOS transistors are used for RF switches, then manufacturing simplicity is improved, but leakage current and insertion loss worsen
Solution Approach 1:
Different transistor types are used in different stages of the RF switch based on local requirements. The first stage uses transistors optimized for low insertion loss (e.g., with specific W/L ratios and channel lengths), while the second and third stages use transistors optimized for power blocking and isolation. This local optimization of transistor characteristics reduces overall insertion loss while maintaining compatibility with standard CMOS manufacturing processes.
Solution Approach 2:
The substrate body connections are dynamically controlled through switching mechanisms that adjust the electrical characteristics of each transistor stage based on the operating mode (transmit or receive). This dynamic adjustment optimizes the balance between insertion loss and power blocking performance across different operating conditions without requiring separate hardware for each mode.
3Power
If multi-stacked transistor structure is used, then power blocking capability is improved, but device complexity increases
Solution Approach 1:
Multiple transistor stages and substrate body switching functions are merged into a single integrated CMOS device structure. The stacked transistors share common substrate connections and control signals, and the substrate body switching is achieved using the same CMOS transistors that form the signal paths. This merging approach increases power blocking capability while minimizing the increase in device complexity by reusing existing structures for multiple functions.
Data Source
AI summary
Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SPDT switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz, 1.9 GHz and 2.1 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate switching and attachment of external capacitor between drain and gate to block high power signals from the transmit path as well as to maintain low insertion loss at the receiver path. Exemplary embodiments of the CMOS antenna switch may provide for 38 dBm P 0.1 dB at multi bands (e.g., 900 MHz, 1.8 GHz, and 2.1 GHz). In addition, −60 dBc second and third harmonic performance up to 30 dBm input, may be obtained according to example embodiments of the invention.