Planar Vertical FET Integration for I/O Performance
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Solution Overview
Problem
Vertical FETs are not optimized for I/O devices due to their minimal room for long gates, which limits their current density and thermal characteristics, whereas planar FETs are better suited for these applications but not integrated effectively with vertical FETs.
Innovation Solution
A method is developed to integrate a planar FET with a vertical FET by forming a fin, isolating a bottom source/drain region, depositing gate dielectric and metals, and sharing a gate mask for etching both vertical and planar gates, while also growing epitaxy on the top source/drain region and forming silicide regions for contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical FETs are used for logic and memory devices, then device density is improved, but I/O device performance deteriorates due to minimal room for long gates
Solution Approach 1:
The device is segmented into two distinct FET types: vertical FETs for logic/memory functions where high density is critical, and planar FETs for I/O functions where long gate performance is critical. This segmentation allows each FET type to be optimized for its specific function without compromise
Solution Approach 2:
Different regions of the semiconductor device are assigned different FET architectures based on functional requirements. The vertical FET region provides high density for logic/memory, while the planar FET region provides optimized long gate characteristics for I/O operations, creating local quality variations throughout the device
2Reliability
If planar FETs are used for I/O devices, then current density and thermal characteristics are improved, but integration with vertical FETs becomes complex
Solution Approach 1:
The patent merges the fabrication processes for vertical and planar FETs into a unified integrated structure. By combining both FET types in a single device and using shared process steps, the overall integration complexity is reduced compared to implementing them as separate devices
Solution Approach 2:
The integrated device structure serves multiple functions: it houses both vertical FETs for logic/memory and planar FETs for I/O operations within a single semiconductor substrate, allowing one device to perform multiple functions that would otherwise require separate components
3Quantity of substance
If vertical FETs with short gates are used, then device density is maximized, but thermal management and current density deteriorate
Solution Approach 1:
The device segments thermal management functions between vertical and planar FET regions. The planar FETs with their superior thermal characteristics handle functions requiring better heat dissipation, while vertical FETs handle functions where density is paramount and thermal requirements are less critical
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integration scheme optimizes the performance of both planar and vertical FETs for memory, logic, and I/O devices by enabling the integration of long gate lengths in a short gate length device, improving process control and reducing costs.
Implementation Method 1
growing epitaxy on a top S/D region
Data Source
AI summary
One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.