Semiconductor Contact Hole Formation via Spacer Patterning
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Solution Overview
Problem
Conventional photolithography processes face difficulties in forming contact holes with very narrow spaces, widths, or diameters in semiconductor devices, often resulting in unnecessary pattern formation in edge and peripheral areas during fine pattern formation using techniques like double patterning, quadruple patterning, and direct self-assembly processes.
Innovation Solution
A method involving the formation of a target layer with a cell area and edge area, a stopper layer, and a hard mask with specific openings and trenches, followed by the creation of pillar patterns and polymer blocks to selectively form contact holes only in the cell area while avoiding the edge and peripheral areas, using techniques such as forming opening spacers, etching, and removing specific layers to prevent pattern formation in these areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography processes are used to form contact holes, then the manufacturing process is simple, but it is difficult to form contact holes with very narrow spaces, widths, or diameters
Solution Approach 1:
The patterning process is divided into multiple stages: first forming a mandrel pattern, then using it to create spacers, removing the mandrel, and repeating the process to form the final contact hole pattern. This segmentation allows each stage to be optimized independently, achieving narrow contact hole dimensions while maintaining process control
Solution Approach 2:
The mandrel pattern is formed in advance as a template before the actual contact hole pattern is created. This preliminary structure guides the subsequent spacer formation and material deposition, enabling precise positioning of narrow contact holes without requiring direct patterning at the final dimensions
2Manufacturing precision
If double patterning, quadruple patterning, or direct self-assembly processes are used to form fine patterns, then contact holes with narrow spaces can be formed, but unnecessary patterns are formed in the edge area and/or peripheral area
Solution Approach 1:
Different regions of the substrate are treated differently: the cell area receives the full multi-stage patterning treatment to form narrow contact holes, while the edge and peripheral areas are protected or selectively processed to prevent unnecessary pattern formation. This localized approach ensures fine patterning where needed without creating harmful patterns elsewhere
Solution Approach 2:
The harmful unnecessary patterns formed in edge and peripheral areas are selectively removed or prevented from forming in the first place through region-specific processing. The cell area is isolated and processed separately to maintain the desired contact hole pattern while eliminating unwanted patterns in non-cell regions
Data Source
AI summary
Methods of fabricating a semiconductor device are provided. The methods may include forming a stopper layer on a target layer including a cell area and an edge area, forming a hard mask including first upper openings and dam trench on the stopper layer, forming opening spacers on inner walls of the first upper openings and a dam pattern in the dam trench, removing the stopper layer exposed in the first upper openings to form first lower openings, forming pillar patterns in the first lower openings and the first upper openings and an eaves pattern on the dam pattern, removing the hard mask in the cell area, forming a first polymer block between the pillar patterns including second upper openings, etching the stopper layer exposed in the second upper openings to form second lower openings, and removing the first polymer block, the pillar patterns, the dam pattern and the eaves pattern.