Semiconductor Contact Plug via Dual Stop Layers
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Solution Overview
Problem
Conventional FinFET fabrication faces issues with direct penetration of contact plugs through metal gates, affecting device performance due to optical constraints, which complicates the integration of metal gates and contact plugs.
Innovation Solution
A method involving four photo-etching processes is employed to form openings in dielectric layers, allowing for precise exposure and removal of stop layers to create contact plugs that electrically connect to both source/drain and gate structures, thereby improving the integration of metal gates and contact plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional photo-etching processes are used to form contact plugs, then the fabrication process is simple, but direct penetration of contact plugs through metal gates occurs affecting device performance
Solution Approach 1:
The patent divides the single etching process into four separate photo-etching processes, each forming openings in different dielectric layers independently. This segmentation prevents direct penetration of contact plugs through metal gates by controlling each etching step to stop at appropriate stop layers, thereby improving device performance while managing fabrication complexity through systematic process division.
Solution Approach 2:
The patent introduces stop layers (first and second stop layers) before forming the contact plugs. These stop layers are prepared in advance to control the etching depth and prevent over-etching that would cause direct penetration. By performing this preliminary action of creating depth control structures, the patent ensures reliable device performance while maintaining a manageable fabrication process.
2Manufacturing precision
If four photo-etching processes are used to form openings in dielectric layers, then contact plug penetration is prevented, but the fabrication process becomes more complex
Solution Approach 1:
The patent segments the contact plug formation into four distinct photo-etching processes, each targeting a specific dielectric layer with its own mask and etching parameters. This segmentation achieves precise contact plug positioning by controlling each etching step independently with appropriate stop layers, while the modular nature of segmented processes makes the increased complexity manageable through systematic organization.
Solution Approach 2:
The patent uses stop layers as intermediary structures between the metal gate and the contact plugs. These stop layers act as mediators that control the etching process, ensuring that contact plugs are formed with precise positioning without directly penetrating the metal gate. The intermediary stop layers absorb the complexity of depth control, allowing precise positioning to be achieved while maintaining a structured fabrication process.
3Reliability
If contact plugs are formed to electrically connect to gate structures, then device performance improves, but optical constraints are exacerbated
Solution Approach 1:
The patent resolves the optical constraint issue by transitioning from a single-layer contact structure to a multi-layer dielectric structure with four separate opening formation processes. This dimensional change in the contact plug architecture allows electrical connection to gate structures to be achieved through vertical stacking and selective etching, bypassing the optical constraints that would affect planar or single-layer contact formation. The multi-dimensional approach enables reliable electrical connections while avoiding the harmful optical interference.
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.


