Semiconductor Capacitor Formation via Selective Etching
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Solution Overview
Problem
As semiconductor device integration increases, the narrow spaces between patterns and the need for precise etching of layers pose challenges in forming capacitors and electrodes with high integration density and effective material selectivity.
Innovation Solution
A method involving the formation of a semiconductor device through a series of layered structures and selective etching processes using different etchants to expose and isolate electrode surfaces, allowing for the formation of capacitors with high integration density and precise control over material removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration of semiconductor device increases, then device density is improved, but space between patterns becomes narrow making precise etching difficult
Solution Approach 1:
The patent divides the etching process into multiple stages by introducing different molding layers (first molding layer, second molding layer) with distinct etch selectivities. Each layer is selectively removed in sequence to expose specific regions, enabling precise control over etching depth and location in high-density device structures.
Solution Approach 2:
The patent uses molding layers as intermediary structures that facilitate selective etching. These intermediate layers act as masks and spacers that enable precise pattern transfer and electrode formation in narrow spaces without directly interfering with the final device structure.
2Quantity of substance
If multiple layers are formed to achieve high integration density, then device functionality is improved, but process complexity increases
Solution Approach 1:
The molding layers serve multiple functions simultaneously: they act as etch masks, spacers for electrode positioning, and templates for pattern formation. This multi-functionality reduces the need for separate dedicated structures, simplifying the overall process despite high integration density requirements.
Solution Approach 2:
The patent utilizes changes in material properties (etch selectivity, removal conditions) of different molding layers to achieve selective etching. By controlling etching parameters such as etchant type and processing conditions, the complex multi-layer structure is managed through systematic parameter variation rather than increasing structural complexity.
3Manufacturing precision
If selective etching is performed to expose electrode surfaces, then capacitor formation precision is improved, but material selectivity requirements increase
Solution Approach 1:
The patent assigns different etch selectivity properties to different molding layers (first molding layer with first etch selectivity, second molding layer with second etch selectivity). This local differentiation of material properties enables selective removal of specific layers while preserving others, achieving precise capacitor formation without requiring universal material properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of semiconductor devices with high integration density and effective capacitor formation, achieving low leakage current and superior on/off current characteristics.
Implementation Method 1
The upper molding layer is formed of material that has an etch selectivity with respect to the lower molding layer. Accordingly, the upper molding layer is removed using a first etchant that does not etch the lower molding layer
Implementation Method 2
the lower molding layer is removed with a different type of etchant
Data Source
AI summary
A method of forming semiconductor device includes forming a landing pad, forming a stopping insulating layer on the landing pad, forming a lower molding layer including a first material on the stopping insulating layer, forming an upper molding layer including a second material different from the first material on the lower molding layer, forming a hole vertically passing through the upper molding layer and the lower molding layer and exposing the landing pad, forming a first electrode in the hole, removing the upper molding layer to expose a part of a surface of the first electrode, removing the lower molding layer to expose another part of the surface of the first electrode, forming a capacitor dielectric layer on the exposed parts of the surface of the first electrode, and forming a second electrode on the dielectric layer.