3D NOR-P Memory Devices With Vertical Bit-Line Pillars
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Solution Overview
Problem
In three-dimensional integrated circuit (3D IC) devices, the performance and functionality are limited by degrading wire interconnects due to scaling, which affects power consumption and efficiency, and existing 3D stacking techniques face challenges in reducing wire lengths and improving retention time, write/erase speed, and power efficiency.
Innovation Solution
The development of 3D NOR-P memory devices with vertically oriented bit-line pillars directly connected to memory transistors, featuring a channel with a circular or ellipsoidal shape, crystallized polysilicon, and a thermal path for heat removal, along with the use of metal atoms for partial metallic properties and Schottky barrier source/drain configurations to enhance carrier generation and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling is applied to reduce component sizes, then transistor performance and density improve, but wire interconnect performance degrades
Solution Approach 1:
The patent transitions from planar 2D interconnect architecture to three-dimensional interconnect architecture with vertical pillars extending through multiple memory layers. This dimensional change allows direct vertical connections between bit lines and memory cells across stacked layers, eliminating the need for lengthy lateral wire interconnects that degrade with scaling. The vertical pillar structure maintains reliable electrical connections while enabling continued transistor scaling.
2Device complexity
If conventional 3D stacking techniques are used, then layer integration is achieved, but wire lengths are not sufficiently reduced
Solution Approach 1:
The patent segments the interconnect structure into vertical bit-line pillars that extend through multiple memory layers, with each pillar serving as a dedicated vertical interconnect for specific memory cells. This segmentation allows direct vertical access to memory cells in each layer, eliminating the need for long lateral wire interconnects that would be required in conventional stacked architectures. The segmented pillar structure achieves both high layer integration and minimal effective wire length.
3Productivity
If wire interconnects are scaled down, then component density increases, but power consumption increases due to degraded wire performance
Solution Approach 1:
The patent employs vertical pillar structures that provide direct through-layer connections, dramatically reducing the effective current path length compared to lateral wire interconnects. This dimensional change reduces resistive power losses (I²R) in the interconnect structure, enabling continued component scaling without the power consumption penalty that would otherwise result from degraded wire performance at scaled dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces wire lengths, improves retention time, write/erase speed, and power efficiency, enabling wider bus width applications and lower power consumption, suitable for high-capacity DRAM and mobile devices.
Implementation Method 1
a thermal path from the bit-line pillars to an external surface of the device to remove heat
Implementation Method 2
each of the plurality of the bit-line pillars includes metal atoms such that the plurality of bit-line pillars have at least partial metallic properties
Data Source
AI summary
A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel is isolated from another channel disposed directly above the channel.