3D NOR Memory Vertical Gate Structures Random Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensionally stacked NAND flash memory devices offer higher density but lack random access and operating speed, while planar NOR flash memory is limited in density and speed.
Innovation Solution
A random access 3D NOR memory device with vertical gate structures, comprising stacks of bit lines alternating with insulating strips and vertical gate structures, allowing for vertical channel structures and memory elements between the gates and insulating strips, enabling channels between bit lines and separate word line transistors and word lines for efficient memory cell selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally stacked NAND flash memory is used, then storage density is improved, but operating speed and random access capability deteriorate
Solution Approach 1:
The patent transitions from planar 2D memory architecture to 3D vertical architecture by stacking multiple bit line layers (first bit line layer, second bit line layer, third bit line layer) vertically. Memory cells are formed at intersections of vertical channel structures with bit lines in different layers, enabling three-dimensional arrangement of memory elements while maintaining random access capability through vertical gate structures that can independently control channels in different layers.
2Quantity of substance
If three-dimensionally stacked NAND flash memory is used, then storage density is improved, but random access capability deteriorates
Solution Approach 1:
The patent divides the memory structure into multiple independently controllable segments through vertical gate structures. Each vertical gate structure can be independently controlled to select specific memory cells in different layers, enabling random access to any memory cell location. The bit lines are segmented into multiple layers with insulating layers between them, allowing independent addressing and selection of memory cells in different vertical positions.
3Manufacturing precision
If vertical gate structures with separated word line transistors are used, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent moves the word line transistor structures from the planar plane to the vertical dimension. Word line transistor channel structures are formed extending vertically, with source and drain regions positioned at different vertical levels. This vertical arrangement allows independent formation and precise alignment of word line transistors with their corresponding vertical channel structures, improving manufacturing precision while the modular vertical design actually reduces overall device complexity compared to planar configurations.
Data Source
AI summary
A memory device comprises a plurality of stacks of bit lines alternating with insulating strips over an insulating layer on a substrate, and a plurality of vertical gate structures disposed between the stacks. Vertical channel structures and memory elements are disposed between outside surfaces of the vertical gate structures and sidewalls of insulating strips in the stacks of bit lines. The vertical channel structures provide channels between adjacent bit lines in the stacks. A plurality of word line transistors is disposed over and connected to respective vertical gate structures. A plurality of word lines is disposed over and connected to the word line transistors. The memory device comprises circuitry connected to the bit lines to apply bit line and source line voltages to the bit lines.