3D NOR Memory Vertical Source Drain Structures
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Solution Overview
Problem
Current memory devices face limitations in achieving high density, random access, and operating speed, particularly in three-dimensionally stacked NAND flash memory technologies, which are either non-random access or have lower speed compared to planar NOR flash memory.
Innovation Solution
A random access 3D NOR memory device is designed with vertical source and drain structures, featuring stacks of word lines alternating with insulating strips and trenches, where vertical conductive structures act as source/drain conductors, and multi-layer films of memory and channel materials are disposed on the sidewalls of word lines, enabling ohmic contact and isolation through recessed insulating material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally stacked NAND flash memory is used to achieve higher density, then storage capacity increases, but random access capability is lost and operating speed decreases
Solution Approach 1:
The patent transitions from planar 2D memory architecture to 3D vertical architecture by stacking multiple memory layers vertically. Word lines are arranged in multiple stacked layers (WL1, WL2, WL3, etc.) extending in the vertical direction, while bit lines extend horizontally, creating a three-dimensional memory structure that increases storage capacity while maintaining random access through vertical channel formation
Solution Approach 2:
The memory structure is segmented into multiple independent memory layers stacked vertically, with each layer containing word lines, channel structures, and memory materials. The vertical channels divide the memory into discrete segments that can be independently accessed, enabling random access capability in the 3D structure
2Quantity of substance
If three-dimensionally stacked NAND flash memory is used to achieve higher density, then storage capacity increases, but operating speed decreases
Solution Approach 1:
By transitioning to 3D vertical stacking with vertical channels extending through multiple word line layers, the patent reduces the lateral distance electrons must travel compared to planar structures. The vertical channel architecture allows for shorter channel lengths and faster electron transport, maintaining high operating speed while achieving higher density through vertical stacking
3Reliability
If vertical conductive structures are disposed in trenches between stacks, then isolation of word lines is improved, but device complexity increases
Solution Approach 1:
Insulating material is introduced as an intermediary substance filling the trenches between vertical conductive structures. This insulating material acts as a mediator that electrically isolates adjacent word lines and vertical channels, preventing unwanted current leakage and crosstalk while maintaining a relatively simple overall device structure
Solution Approach 2:
The patent extracts the isolation function from the bulk material and concentrates it in specific trench regions filled with insulating material. By removing conductive material from trench areas and replacing it with insulating material, the design achieves effective electrical isolation without requiring complex isolation structures throughout the entire device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the formation of high-density arrays with random access capabilities and enhanced operating speed by isolating word lines from vertical conductive structures, enabling efficient selection and operation of memory cells.
Implementation Method 1
The channel material extends between, and makes ohmic contact with, adjacent vertical conductive structures. As used herein, ohmic contact is a low resistance junction providing current conduction between the channel material and the vertical conductive structures.
Data Source
AI summary
A memory device comprises a plurality of stacks of word lines alternating with insulating strips, the stacks being separated by trenches, the word lines extending in a first direction. A plurality of columns of vertical conductive structures is disposed in the trenches between adjacent stacks. Multi-layer films of memory material and channel material are disposed on sidewalls of word lines on at least one side of the trenches between adjacent vertical conductive structures in the plurality of vertical conductive structure, the channel material in ohmic contact with the vertical conductive structures. At locations of vertical conductive structures in the plurality of vertical conductive structures, the sidewalls of the word lines are recessed between insulating strips in the stacks to form recesses on the sidewalls of the word lines to isolate the word lines from vertical conductive structures.