3D NOR Array Shared Source-Drain Pillars
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Solution Overview
Problem
Current NOR memory devices face challenges in achieving high storage density and fast access speeds due to the need for separate bit lines and source/drain pillar structures for each memory cell, which limits their compactness and efficiency.
Innovation Solution
A three-dimensional semiconductor structure is developed with vertically-alternating stacks of insulating and conductive strips, laterally-alternating semiconductor channels and source/drain pillar structures, and memory films, where each source/drain pillar is in direct contact with a pair of semiconductor channels, enabling shared source/drain regions and word lines across multiple memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate bit lines and source/drain pillar structures are provided for each memory cell, then direct access to memory cells is enabled, but device area and complexity increase
Solution Approach 1:
The patent merges source/drain pillar structures by enabling them to be shared between adjacent memory cell strings. Specifically, a source/drain pillar structure can serve as the source for one memory cell string and the drain for an adjacent string, eliminating the need for separate source/drain pillars for each string. This sharing approach directly reduces device area while maintaining the parallel access capability that provides fast read/write speeds.
Solution Approach 2:
The patent implements multi-functionality where single source/drain pillar structures perform multiple functions by serving different memory cell strings. These shared source/drain regions act as source for some cells and drain for others, allowing the same physical structure to fulfill multiple electrical roles. This universality reduces the total number of components needed while preserving direct access performance.
2Speed
If separate source/drain pillar structures are used for each memory cell, then direct access is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple source/drain pillar structures into shared regions that serve adjacent memory cell strings. This merging reduces the total number of discrete structures that need to be formed, aligned, and doped separately, thereby simplifying the manufacturing process while maintaining the fast access characteristics of direct-connection NOR memory cells.
3Quantity of substance
If vertically-alternating stacks of insulating and conductive strips are implemented, then storage density increases, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the memory structure into vertically-stacked repeating units, where each unit contains insulating strips and conductive strips arranged in alternating sequences. This segmentation into modular units allows for systematic fabrication using repeated deposition and etching cycles, making the complex three-dimensional structure more manufacturable while achieving high storage density through vertical stacking.
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking. By stacking multiple memory cell strings vertically with alternating insulating and conductive strips, the device achieves higher storage density in the vertical dimension. The manufacturing process handles this complexity through sequential layer formation and patterning, making the 3D structure feasible to produce.
Data Source
AI summary
A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.