3D Non-Volatile Memory Device Junction Interface Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional non-volatile memory (NVM) devices face challenges in achieving consistent electrical characteristics due to variations in polysilicon field oxide height (PFH) of transistors, which affect the integration density and performance of semiconductor memory devices.
Innovation Solution
A method involving the alternately formation of insulating and conductive gates on a semiconductor substrate, followed by the creation of a stack structure, contact holes, and precise etching of gap-fill insulating layers to define junction regions, with diffusion-preventing ions implanted to control impurity diffusion and capping layers formed to enhance junction integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing methods are used for 3D NVM devices, then the basic device structure can be formed, but variations in polysilicon field oxide height (PFH) occur which degrade electrical characteristics
Solution Approach 1:
The method performs preliminary etching of the gap-fill insulating layer to define a preliminary junction region before forming the final junction. This preliminary action establishes a controlled reference level that prevents subsequent variations in PFH, thereby improving both manufacturing precision and electrical characteristics consistency
Solution Approach 2:
The gap-fill insulating layer serves as an intermediary material that enables precise junction region definition. By etching this intermediate layer to a target depth to create the preliminary junction region, the method achieves accurate control over the channel layer etching depth, which directly improves PFH consistency and reduces electrical characteristic variations
2Manufacturing precision
If the gap-fill insulating layer is etched to the target depth to define the preliminary junction region, then junction interface positioning is improved, but additional process steps are required
Solution Approach 1:
The preliminary etching of the gap-fill insulating layer creates a pre-defined junction region that serves as an accurate reference for subsequent channel layer etching. This preliminary action ensures precise junction interface positioning while the process steps are integrated into the existing manufacturing flow, managing complexity through systematic process integration
3Reliability
If diffusion-preventing ions are implanted into the channel layer, then impurity diffusion is controlled and junction integrity is improved, but the manufacturing process becomes more complex
Solution Approach 1:
Diffusion-preventing ions act as an intermediary mechanism that blocks impurity diffusion at the junction region. By implanting these ions into the channel layer, the method creates a diffusion barrier that protects junction integrity without requiring fundamental changes to the manufacturing process architecture, thus improving reliability while managing complexity through a targeted process addition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces variations in PFH, improves the reliability and performance characteristics of 3D NVM devices by accurately positioning junction interfaces and preventing impurity diffusion, leading to enhanced manufacturing yield and transistor performance.
Implementation Method 1
Diffusion-preventing ions may be implanted into the channel layer
Implementation Method 2
Diffusion-preventing ions may be implanted into the channel layer
Implementation Method 3
A capping layer with impurities may be formed in the preliminary junction region
Data Source
AI summary
In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.