Solid-State Devices TRIZ Cases

Bond wire inductors and an inshin network reduce electromagnetic coupling and compensate for output impedance changes on silicon substrates.

Tandem white and blue diodes emit light without color filters, boosting color gamut while lowering power consumption.

Aqueous conductive polymers replace organic solvents to coat optical films, maintaining quality while reducing manufacturing costs.

A p-channel trench MOSFET uses heavily doped (110) silicon and a high dielectric constant gate layer to increase hole mobility.

Silicon carbide betavoltaic batteries maximize power density by expanding radioisotope surface area to overcome low conversion efficiency.

A FDSOI fabrication method deposits an oxide film on contact hole sidewalls to adjust the physical dimensions of the holes.

A display panel notch filled with silicon nitride blocks water vapor and oxygen ingress to protect internal components.

Shared transport materials in the yellow-green layer reduce inventory while maintaining luminous efficiency and color gamut.

Segmented mask layers with crossing openings enable precise etching of high-aspect-ratio memory trenches without mask deformation.

Source lines in X and Y directions connect to a protruding gate layer, reducing gate density to enhance breakdown voltage.

A semiconductor device integrates resistors with different resistances using selective ion diffusion and silicide layers.

Segmenting N-type deep well regions lowers parasitic capacitance, enabling effective electrostatic discharge protection in high-speed radio frequency circuits.

Detecting structural tapering in 3D memory layers enables adaptive error correction codes that compensate for bit errors.

An insulating heat conducting layer connects to scan lines and electrodes in an OLED panel to move thermal energy away from the light emitting structure.

Non-uniform surface treatment of photoresist patterns enables selective strip solution infiltration to form pixel electrodes on display substrates.

A light-concentrating layer with protrusions focuses laser energy onto amorphous semiconductor patterns to drive efficient crystallization.

Orthorhombic hafnium oxide gate insulator with laminated titanium nitride and tungsten conductive layers.

A display window integrates a light shielding layer with protrusions to prevent polarizer end portion visibility while maintaining luminance.

Combining a metal nanowire grid with a transparent conducting oxide matrix reduces leakage current and shorting while maintaining high optical transparency.

Ferrite barrier blocks interference while diode routes signals for authentication, preventing unauthorized peripheral use without adding complexity.

A light-emitting device uses a reflective member below the resin to enhance optical output.

Transfer semiconductor layer onto support with weakening pattern to cut individual chips, avoiding flaking and rigidity issues from direct scribing.

A semiconductor image sensor uses a global shutter mechanism to synchronize pixel exposure timing.

Shifting adjacent SRAM cell areas reduces the total layout footprint by 3.0% or expands it to improve manufacturing yield rates.

Supporting layers connect non-emissive substrate regions to prevent organic EL layer damage from bending stress.

Self-aligning molds enable economical fabrication of carbon nanotube antennas, resolving high manufacturing costs while maintaining efficient energy conversion.

A segmented ferroelectric layer uses distinct crystal orientations to isolate active storage regions from adjacent cells.

Vertical vias in close-packed LED arrays conduct heat to a dedicated substrate, enabling high current density operation without overheating.

A vertical high-voltage LED structure reverses adjacent diode polarities via laser stripping and die bonding on an insulating substrate.

Cone-shaped microstructures redirect incident light to boost intensity at photodetectors, resolving low absorption limits in infrared and red sensing.

Silicon carbide layers suppress thermal diffusion of ions in vertical pn diodes, reducing leakage current without increasing device height.

Central via with elongated conductive strip merges adjacent memory cells to resolve cavity formation challenges at high density.

A copper line cleaning method uses a specific pH solution to remove post-etch residues without damaging the conductive structure.

An electrostatic resistant layer on a display substrate dissipates static charges generated by roller friction, protecting functional film layers from damage.

Bottom-up selective oxide filling resolves cavity and seam issues in sub-100 nm trenches, ensuring reliable isolation.

Undoped InGaN layers facilitate hole injection into the active layer of a nitride semiconductor light emitting element.

Direct deposition of a single semiconductor channel layer eliminates interface states that scatter charge carriers and reduce mobility.

Vertical gate-all-around transistors enable a three-dimensional bitline architecture that reduces resistance and coupling capacitance in SRAM arrays.

Reverse metal layers dissipate driver IC heat, preventing thermal deterioration of self-light-emitting elements.

Maskless laser ablation selectively removes anti-moisture insulation from OLED pads, eliminating alignment defects and reducing PECVD equipment costs.

Penetrating hole in holder equalizes internal pressure during manufacturing, preventing chip damage from trapped air buildup.

Dividing SRAM driver transistors across separate active regions stabilizes device characteristics and simplifies layout patterning.

Integrating photosensitive chips and functional components into a single encapsulation layer reduces module size while improving signal transmission speed.

Curved phosphor-resin interfaces in an LED package resolve the trade-off between light diffusion quality and compact package height.

Conductive spacers isolate floating gates to minimize cell interference and enhance coupling ratio without damaging tunnel oxide films.

Vertical isolation element resolves thermal conductivity trade-off by combining dielectric material with thermal conductive layer for effective heat removal.

Replacing metal interconnects with a polysilicon layer minimizes etch damage to the photodiode crystal structure, reducing dark current and junction leakage.

Apertures in source and drain electrodes expose the oxide semiconductor layer for direct oxygen supply during annealing.

A TFT pixel structure uses substrate bumps to form an uneven reflective layer surface during standard fabrication steps.

Hydrogen plasma treatment creates oxygen vacancies in doped hafnium oxide films to enhance ferroelectric properties.