Solid-State Devices TRIZ Cases

Bond wire inductors and an inshin network reduce electromagnetic coupling and compensate for output impedance changes on silicon substrates.

Tandem white and blue diodes emit light without color filters, boosting color gamut while lowering power consumption.

Aqueous conductive polymers replace organic solvents to coat optical films, maintaining quality while reducing manufacturing costs.

A p-channel trench MOSFET uses heavily doped (110) silicon and a high dielectric constant gate layer to increase hole mobility.

Silicon carbide betavoltaic batteries maximize power density by expanding radioisotope surface area to overcome low conversion efficiency.

A FDSOI fabrication method deposits an oxide film on contact hole sidewalls to adjust the physical dimensions of the holes.

A display panel notch filled with silicon nitride blocks water vapor and oxygen ingress to protect internal components.

Shared transport materials in the yellow-green layer reduce inventory while maintaining luminous efficiency and color gamut.

Segmented mask layers with crossing openings enable precise etching of high-aspect-ratio memory trenches without mask deformation.

Source lines in X and Y directions connect to a protruding gate layer, reducing gate density to enhance breakdown voltage.

A semiconductor device integrates resistors with different resistances using selective ion diffusion and silicide layers.

Segmenting N-type deep well regions lowers parasitic capacitance, enabling effective electrostatic discharge protection in high-speed radio frequency circuits.

Detecting structural tapering in 3D memory layers enables adaptive error correction codes that compensate for bit errors.

An insulating heat conducting layer connects to scan lines and electrodes in an OLED panel to move thermal energy away from the light emitting structure.

Non-uniform surface treatment of photoresist patterns enables selective strip solution infiltration to form pixel electrodes on display substrates.

A light-concentrating layer with protrusions focuses laser energy onto amorphous semiconductor patterns to drive efficient crystallization.

Orthorhombic hafnium oxide gate insulator with laminated titanium nitride and tungsten conductive layers.

A display window integrates a light shielding layer with protrusions to prevent polarizer end portion visibility while maintaining luminance.

Combining a metal nanowire grid with a transparent conducting oxide matrix reduces leakage current and shorting while maintaining high optical transparency.

Ferrite barrier blocks interference while diode routes signals for authentication, preventing unauthorized peripheral use without adding complexity.

A light-emitting device uses a reflective member below the resin to enhance optical output.

Transfer semiconductor layer onto support with weakening pattern to cut individual chips, avoiding flaking and rigidity issues from direct scribing.

A semiconductor image sensor uses a global shutter mechanism to synchronize pixel exposure timing.

Shifting adjacent SRAM cell areas reduces the total layout footprint by 3.0% or expands it to improve manufacturing yield rates.

Supporting layers connect non-emissive substrate regions to prevent organic EL layer damage from bending stress.

Self-aligning molds enable economical fabrication of carbon nanotube antennas, resolving high manufacturing costs while maintaining efficient energy conversion.

A segmented ferroelectric layer uses distinct crystal orientations to isolate active storage regions from adjacent cells.

Vertical vias in close-packed LED arrays conduct heat to a dedicated substrate, enabling high current density operation without overheating.

A vertical high-voltage LED structure reverses adjacent diode polarities via laser stripping and die bonding on an insulating substrate.

Cone-shaped microstructures redirect incident light to boost intensity at photodetectors, resolving low absorption limits in infrared and red sensing.

Silicon carbide layers suppress thermal diffusion of ions in vertical pn diodes, reducing leakage current without increasing device height.

Central via with elongated conductive strip merges adjacent memory cells to resolve cavity formation challenges at high density.

A copper line cleaning method uses a specific pH solution to remove post-etch residues without damaging the conductive structure.

An electrostatic resistant layer on a display substrate dissipates static charges generated by roller friction, protecting functional film layers from damage.

Bottom-up selective oxide filling resolves cavity and seam issues in sub-100 nm trenches, ensuring reliable isolation.

Undoped InGaN layers facilitate hole injection into the active layer of a nitride semiconductor light emitting element.

Direct deposition of a single semiconductor channel layer eliminates interface states that scatter charge carriers and reduce mobility.

Vertical gate-all-around transistors enable a three-dimensional bitline architecture that reduces resistance and coupling capacitance in SRAM arrays.

Reverse metal layers dissipate driver IC heat, preventing thermal deterioration of self-light-emitting elements.

Maskless laser ablation selectively removes anti-moisture insulation from OLED pads, eliminating alignment defects and reducing PECVD equipment costs.

Penetrating hole in holder equalizes internal pressure during manufacturing, preventing chip damage from trapped air buildup.

Dividing SRAM driver transistors across separate active regions stabilizes device characteristics and simplifies layout patterning.

Integrating photosensitive chips and functional components into a single encapsulation layer reduces module size while improving signal transmission speed.

Curved phosphor-resin interfaces in an LED package resolve the trade-off between light diffusion quality and compact package height.

Conductive spacers isolate floating gates to minimize cell interference and enhance coupling ratio without damaging tunnel oxide films.

Vertical isolation element resolves thermal conductivity trade-off by combining dielectric material with thermal conductive layer for effective heat removal.

Replacing metal interconnects with a polysilicon layer minimizes etch damage to the photodiode crystal structure, reducing dark current and junction leakage.

Apertures in source and drain electrodes expose the oxide semiconductor layer for direct oxygen supply during annealing.

A TFT pixel structure uses substrate bumps to form an uneven reflective layer surface during standard fabrication steps.

Hydrogen plasma treatment creates oxygen vacancies in doped hafnium oxide films to enhance ferroelectric properties.

A dual-purpose GIS network uses mobile devices to collect geo-spatial data via a dedicated application.

Composite electrode structure with reflective conductive layer and oxide stabilizer prevents corrosion while enhancing light extraction efficiency.

Segmenting the SSL switch materials prevents threshold-voltage shifts during programming, reducing power consumption in 3D NAND arrays.

A solution composition using zinc, indium, and magnesium compounds forms oxide thin films with improved solubility and uniformity.

Vertical shielding isolates storage diodes to enable global shutter and autofocus without adding complexity.

Segmented wall parts constrain bonding material spreading to prevent protrusion and improve cutting accuracy.

A donor substrate with a peripheral trench receives a selective barrier material on the exposed circuit layer before bonding to a receiver substrate.

A display substrate uses penetration holes filled with bonding material to connect switch devices and displaying units across different sides.

A memory device uses a split gate structure with high-k metal gates to enhance functional density.

A spacing layer with a wide bandgap compound separates excitons in an OLED emission area to prevent material deterioration.

A reinforced insulation film connects adjacent gate electrodes to physically support the structure while a porous interlayer dielectric reduces parasitic capacitance.

A first electrically conductive connection member bridges a TFT drain and photosensitive members to maintain a smooth surface.

A light emitting device package uses a reflective insulating layer to enhance light extraction efficiency.

Mirror-symmetrical sub-pixels in repetitive units alleviate color edge phenomena by ensuring multiple colors are present at the display panel edges.

Segmenting the organic insulator at pad portions reduces contact hole height, preventing disconnection issues caused by excessive passivation layer thickness.

Insulating bank structures prevent solution spilling during inkjet printing, maintaining uniform active layer thickness and minimizing emission area loss.

Interleaved parallel fingers in a compound varactor minimize die area by stacking pairs vertically, resolving the linearity versus footprint trade-off.

A half-in-cell array substrate embeds sensing thin-film transistors between the substrate and packaging layer while positioning sensing units externally.

Segregating drive transistors into an insulated region reduces chip area and simplifies manufacturing by relaxing alignment precision.

An organic light emitter integrates with an inorganic photodetector on a single CMOS substrate to form a monolithic reflex coupler.

Liquid flow generates suction force to separate temporary substrate, reducing chemical consumption and equipment costs.

Nickel-platinum silicide layers form on gate electrodes and source-drain regions using distinct heat treatments to optimize device structure.

Vertical SRAM tag circuitry aligns with DRAM cells in a monolithic die, reducing memory array footprint while increasing retrieval speed.

A mold structure with alternating sacrificial and insulating layers enables vertical memory cell formation in three-dimensional semiconductor devices.

Titanium wetting layers resolve interface contradictions in n-type CNT FETs, increasing average drive currents from 0.46 μA to 0.77 μA.

Pre-placed dummy flipflops reduce interconnect modifications during circuit updates, suppressing clock skew and crosstalk.

Self-assembled monolayers bond to organic semiconductor surfaces, reducing environmental sensitivity while maintaining ease of manufacture.

Gap-fill insulating layer etching defines preliminary junction regions in 3D NVM devices, reducing polysilicon field oxide height variations.

Adjusting dimensions of series resistors with opposing temperature coefficients cancels resistance drift, maintaining uniformity despite thermal fluctuations.

A tunnel oxide layer forms an upper nitride film using plasma nitration and a lower nitride film through thermal nitration.

Segmented wavelength conversion elements with non-penetrating trenches prevent optical crosstalk between adjacent pixels, maintaining high contrast ratios.

Self-assembled monolayers prevent encapsulation layer formation on contact sections, eliminating laser ablation damage to thin metal electrodes.

Optimized transparent photoresist thicknesses create micro cavities that boost red, green, and blue light emission efficiency in COA WOLED structures.

Inner and outer data pad placement with complementary transistors eliminates excess regions to reduce chip size while minimizing noise interference.

Backside contact formation on thinned bulk substrates reduces parasitic capacitance and source/drain resistance.

An organic compound with specific constitutional units enhances power conversion efficiency in photovoltaic cells.

A metal-insulator-metal capacitor uses a Ta2O5/Al2O3/Ta2O5 insulator stack to achieve high electrical capacitance.

Stacked lanthanum aluminum silicate and silicon oxide films suppress leakage currents in nonvolatile memory devices.

Step-like energy band alignment in an OLED device resolves suboptimal luminance performance by enabling superior electron-hole recombination efficiency.

Epitaxially growing semiconductor active regions vertically to form monolithic three-dimensional NAND strings with stacked memory cells.

A tacky layer between substrates absorbs external impacts to protect organic light emitting elements.

An OLED mask forms organic film edges at acute angles, preventing uneven metal deposition and reducing resistance issues during fabrication.

A buried field plate reduces peak electric fields in the drift region of a GaN HEMT, improving switching performance and current stability.

Notch filtering materials create spectral notches in solid state lighting devices to enhance color rendering index and gamut area values.

Segmented barriers with reflecting and transmitting regions extend the light path to improve resolution without reducing light emission.

A semiconductor device uses multilevel wiring to distribute power supply lines across different layers, enabling efficient voltage management.

Insulating cooling element with high thermal conductivity covers contact side, preventing solder overflow between spaced elements.

Refractive dispersive elements replace absorptive filters to boost light use efficiency and sensitivity without diffraction size constraints.

Metal film blocks ultraviolet radiation from organic sealing materials, preventing aging while maintaining high transmittivity.

A display device uses a half-tone mask to pattern conductive and semiconductor layers simultaneously.

Calibration circuits generate codes to synchronize data output across stacked semiconductor chips, resolving timing inconsistencies from process variations.

Segmented anode conductive layers allow targeted material injection, reducing mura defects and improving thickness uniformity.

Merging transistor and capacitor doping masking into one step simplifies OLED manufacturing while improving capacitor efficiency.

A display panel embeds a light filtering part within an accommodating hole of the driving part's insulating layer to reduce height differences.

Discrete doped regions approximate graded profiles to control capacitance, resolving manufacturing complexity while maintaining high Q factor performance.

A tunable resistive element uses a piezoelectric layer to apply mechanical stress for precise resistance control.

A write pulse control block manages resistance paths between global word lines and memory cells using high resistance and bypass circuits.

A dummy pattern layer below memory cell wirings functions as an etching stopper to reduce material removal during manufacturing.

Connection electrodes guide bottom contacts to the top surface, reducing bonding difficulty and improving reliability for micro light emitting diodes.

A power semiconductor circuit uses a diac and Zener element to clamp collector-gate voltage for rapid overvoltage protection.

Directly mounting unpackaged LED chips on conductors reduces manufacturing costs while eliminating bright spots and improving thermal dissipation.

Dual doped hole injection layers and 0.2 eV HOMO alignment reduce power consumption and extend mass production lifetime.

Soluble polyimide with ether bonds withstands high temperature TFT processes while maintaining transparency.

Shared pull-up and pull-down diodes reduce voltage drop and layout area.

Oblique sensing pattern arrangements maintain uniform capacitance and linearity during tilted active pen inputs.

Positioning data lines at subpixel boundaries eliminates black matrix overlap, increasing pixel aperture ratio and transmittance.

OLED pixel regions use specific upper electrode to organic layer thickness ratios to enable microcavity formation via inkjet deposition.

A stacked gate non-volatile memory cell structure with a corner portion covered by an erase gate.

A display panel places connection lines within the active area using vias to link signal paths.

Through holes and embedded electrodes merge optical and electrical connections, reducing module complexity while maintaining reliable signal transmission.

Varying protection layer thickness across subpixels prevents leakage current and enhances light extraction efficiency through micro-cavity effects.

Protrusions on array substrates guide primary spacers to align with substrate features, resolving alignment deviation caused by uneven TFT surfaces.

A protective layer within the insulating layer prevents contacts from connecting to circuit elements below.

A water-absorbing layer completely wrapped by a packaging layer protects light-emitting units.

A touch display panel design places functional units between pixel defining layers to reduce overall thickness.

A shock absorption member uses a layer stack structure to buffer external impacts on an OLED display.

Parallel source line segments lower resistance and power consumption while simplifying MRAM fabrication processes.

A photoresist stripper composition using alcohol amine and glycol ether to dissolve resist coatings without eroding underlying metal lines.

Consolidating word line power connections to one side reduces block size while multi-layer signal wirings mitigate increased capacitance.

A one-pass multilevel programming method uses single pulse sequences to program multiple bits per cell.

A monolithic integrated circuit combines a logic circuit with voltage level shifters to generate modulation signals for power inverter switches.

Segmented phosphor layers on LED chips boost color gamut beyond HDTV standards while maintaining manufacturing reliability.

A single patterning process forms the OLED anode and TFT active layer from one oxide semiconductor sheet.

Stepped bank patterns widen the organic emission layer area, reducing thickness deviations caused by limited nozzle counts in high-definition displays.

A bottom-emission OLED panel places a quantum dot film between the cathode and a reflective isolation layer to optimize light emission.

Segmented insulating films and protective members manage terminal line spacing to prevent residue-induced short circuits in liquid crystal displays.

Alkyl substituents on the fused thiophene core improve solubility and oxidative stability while preserving hole mobility.

A vertical thin film transistor merges the second electrode and gate electrode into a single patterning step to enhance alignment accuracy.

Layered interconnects with varying sheet resistances eliminate protective circuitry requirements, enabling narrower frame designs and higher display resolution.

A U-shaped first electrode surrounds a photodiode gap to concentrate incident light onto the active area.

A tunneling oxide layer positioned between first and second carbon layers blocks electrical current flow in semiconductor memory devices.

Varying organic emission layer thickness on bent substrates compensates for tilting angles, ensuring accurate color reproduction despite structural deformation.

A crystal diffraction lens concentrates gamma radiation onto a small focal region, resolving detection sensitivity limits in nuclear medicine cameras.

A recessed planarizing layer accommodates a dummy light emitting layer within an organic EL display panel structure.

A translucent adhesive layer guides light between elements, reducing attenuation and improving optical intensity uniformity.

High-k and low-k insulating layers in the isolation region inhibit hot electron punch-through while maintaining electrical separation at ultra-fine pitches.

An interposer with flexible structures decouples mechanical stress from the sensor die, reducing damage risk while maintaining a compact package footprint.